At IQM, we build world-leading quantum computers for the well-being of humankind. We design systems to tackle computational challenges beyond the practical limits of classical machines. Our work sits at the edge of science and engineering. It's complex, demanding, and deeply collaborative. We turn deep research into reliable, full-stack systems that drive discoveries in fields like medicine, energy, and technology, reshaping how the world computes.
Join the team that gives quantum a heartbeat.
The work
We are seeking a passionate Quantum Engineer, (Junior to Senior level) to join our Gates team in Espoo, Finland, or Munich, Germany. We are looking for candidates with a strong understanding of quantum gate control, a hands-on approach to problem-solving, and a proactive mindset. You’ll be at the forefront of research and development on quantum gate implementations for our superconducting quantum processors.
What you’ll actually do
- Developing and refining single- and two-qubit gates.
- Creating calibration and characterization routines.
- Analyzing gate fidelities and addressing their physical limitations.
- Collaborating across design, fabrication, software, theory, and other experimental teams to boost QPU performance.
- Contributing to efforts toward full quantum error correction.
- (Senior level) Mentoring junior team members and leading initiatives in technical focus areas.
What we’re looking for
- Junior Quantum Engineer — M.Sc. degree in Physics, Quantum Engineering, or a related field.
- Quantum Engineer—Ph.D. degree in physics or a related discipline, or alternatively equivalent experience in quantum technologies.
- Senior Quantum Engineer — Postdoctoral or equivalent industrial experience in quantum technologies.
- Proven knowledge of gate-based quantum computation.
- Experimental experience with superconducting quantum bits or similar modalities.
- Python development experience (ideally in a quantum control framework).
- Strong analytical, documentation, and communication skills.
- Independent problem-solving abilities and drive to contribute to large-scale R&D.
Nice-to-Have:
- Prior work on randomized benchmarking or other gate fidelity characterization methods.
- Experience with version control and collaborative software development.
- Background in calibration automation or quantum processor benchmarking.
- Experience with cryogenic hardware and technologies.
- For experienced engineers—Strong publication record in superconducting quantum computing, quantum gate control and characterization, or a related field.
Why IQM?
- Full-stack quantum computing: From quantum hardware to software layers and beyond, we build across the full-stack.
- High-performance playground: We aim high, and we know sustainable performance only works when life outside work does too—hybrid setups, flexible hours.
- Never the smartest: Expect to learn constantly. You won't always be the smartest person in the room, and that's the point.
- Approachable leadership: Flat hierarchy, direct access. Feel free to approach any leaders. They're friendlier than they look!
- The sweet spot: Big enough to matter. Small enough to move fast. Growing between a startup and a corporation. We’re in the phase where top performers get noticed.
- Bigger than IQM: Our people build know-how for the entire quantum ecosystem. We publish papers, run hackathons, and help shape a market that's still being defined.
The future of computing won’t build itself. You might be one of the few who do.
We'll start interviews and move forward with hiring as soon as we meet strong candidates. Please submit your application soon.
600M€+ Total Funding | 300+ Team Members | 30+ Quantum Computers Built | 300+ Patents Filed | 10 Location Globally
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The role of a gate-level quantum engineer is a fundamental structural necessity within the hardware layer of the quantum computing value chain, directly driving the transition from noisy intermediate-scale quantum devices to fault-tolerant architectures. By focusing on the precision control, calibration, and optimization of single- and multi-qubit gates, this specialization addresses the critical physics-to-engineering bottleneck that governs overall quantum processor fidelity. Market indicators from national technology roadmaps and consortia emphasize that scaling superconducting quantum processors relies entirely on mitigating gate errors to cross the threshold required for quantum error correction. Consequently, this function acts as a high-leverage stabilization point that translates abstract quantum algorithmic requirements into deterministic, physical machine execution. Ultimately, these engineering advancements secure the underlying reliability needed to support hybrid classical-quantum cloud infrastructures and unlock enterprise-grade computational advantage.
The superconducting quantum computing landscape is experiencing a definitive shift from laboratory validation toward the industrialization of full-stack processing units. In this evolution, the primary technical constraint has moved beyond mere qubit count to the much more demanding metric of logical gate performance and error mitigation. The core challenge within the hardware value chain involves managing the trade-offs between qubit connectivity, coherence times, and control pulse scaling. As systems scale to dozens and eventually hundreds of physical qubits, the complexity of cross-talk and environmental noise introduces significant execution risks that threaten computational reproducibility.
Ecosystem-level analyses indicate that workforce scarcity remains highly acute at the intersection of microwave engineering, cryogenic hardware design, and quantum information science. This talent gap creates a structural dependency, as the pace of hardware optimization is limited by the availability of specialists who can bridge the gap between abstract theoretical physics and practical systems engineering. Current industry focus lies on bridging classical and quantum capabilities at scale, requiring highly mature automated calibration frameworks to replace manual tuning processes that cannot scale to larger processor architectures.
Furthermore, national security mandates and public-private funding initiatives are accelerating the need for standardized benchmarking protocols across diverse hardware modalities. The hardware enablement layer must increasingly interoperate with classical high-performance computing systems, positioning gate-level optimization as the foundational gatekeeper for all high-level software abstraction layers. Consequently, the maturation of gate control methodology is a primary driver for moving technology readiness levels from experimental platforms to commercial quantum-as-a-service deployment.
The capability architecture for this role type centers on the dense synchronization of quantum gate control theory with practical experimental physics and automated systems engineering. Mastery over the software-hardware interface requires deep expertise in developing calibration and characterization routines, such as randomized benchmarking, to precisely isolate and quantify physical error mechanisms within superconducting circuits. This technical proficiency must be tightly coupled with Python-based quantum control frameworks and version-controlled collaborative software development environments to ensure reproducible results across distributed research teams. These capabilities are vital for expanding organizational throughput, as they enable the transition from manual, single-qubit tuning to automated, system-wide optimization matrices. Furthermore, a sophisticated understanding of cryogenic infrastructure and microwave pulse shaping provides the essential leverage needed to manipulate qubit states safely below the error thresholds required for full quantum error correction. By managing these complex hardware dependencies, this engineering function establishes the baseline stability that allows software compilers and high-level programming languages to execute complex quantum algorithms without architectural degradation. - Accelerates the transition from noisy intermediate-scale quantum hardware to scalable fault-tolerant architectures
- Mitigates systemic execution risks by optimizing the fidelity of single- and multi-qubit control operations
- Facilitates the implementation of automated calibration routines to support larger quantum processor scaling
- Strengthens the reproducibility of hardware benchmarks through standardized gate characterization methodologies
- Reduces iteration friction between theoretical quantum physics models and physical processor manufacturing teams
- Optimizes the performance of superconducting qubits by isolating and addressing localized cross-talk mechanisms
- Enhances the stability of full-stack systems by securing high-fidelity baselines at the physical layer
- Supports the integration of quantum processors with classical high-performance computing control infrastructure
- Improves the long-term viability of technology investments by advancing towards full quantum error correction
- Enables the systematic evaluation of physical limitations within next-generation processor architectures
- Protects capital allocation in research by turning abstract control theories into functional hardware capabilities
- Orchestrates cross-functional alignment between design fabrication software and experimental deployment groupsIndustry Tags: Quantum Computing Hardware, Superconducting Qubits, Quantum Gate Control, Calibration Automation, Quantum Error Correction, Microwave Engineering, Cryogenic Infrastructure, Randomized Benchmarking
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