About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for an expert System Modelling Engineer to drive the modelling, integration, and performance analysis of our advanced Vertical Compute / VIMx system memory architectures.
In this role, you will be responsible for building robust SystemC models, integrating them onto the Palladium emulation platform, and benchmarking performance against an ideal SRAM baseline for cutting-edge AI applications.
Key Responsibilities:
- System-Level Modeling: Design, validate, and deliver robust SystemC software models for individual VIMx components and the broader memory hierarchy.
- Multi-Bank Configurations: Model and simulate complex multi-bank system memory configurations to evaluate latency, throughput, and system behavior.
- Emulation Platform Integration: Deploy and configure completed SystemC memory models onto the Cadence Palladium emulation platform.
- Co-Simulation & Validation: Ensure seamless interface and operational stability between the emulation environment and the memory models.
- Performance Evaluation & AI Benchmarking: Execute AI application benchmarks on the Palladium platform.
- Value Demonstration: Deliver a detailed performance evaluation report contrasting the VIM system memory architecture against an ideal SRAM baseline across key metrics (latency, bandwidth, energy efficiency, and area) to prove the benefits of VIM.
About the team:
This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
About who you are:
Technical Expertise:
- Education: BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
- Software Skills: Exceptional programming skills in systemC, TLM, C/C++ and Python for architectural modeling and scripting.
- Architecture Knowledge: Deep understanding of computer architecture, specifically memory hierarchies (caches, SRAM, DRAM, HBM, memory controllers, and interconnects).
- Modeling Experience: Proven track record of developing and validating system-level performance models using SystemC, Qemu, gem5, or similar architectural simulators.
- Emulation Familiarity: Hands-on experience with hardware emulation platforms (e.g., Cadence Palladium, ZeBu, or Veloce) is a strong plus.
Professional skills :
- Strong analytical skills for measuring, interpreting, and presenting architectural performance trade-offs.
- Ability to author clean, comprehensive technical reports for cross-functional hardware and software teams.
- Autonomy and problem-solving mindset in a high-tech R&D environment.
Why Join Us:
- You will get the opportunity to work at the forefront of memory technology innovation.
- Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
- You can be part of a talented and dedicated team in a fast-paced startup environment.
- In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
- You can count on a motivating total rewards package.
- Flexible ways of working.
Join us in shaping the future of compute & memory technology — and celebrating success!
QUANTUM ROLE CONTEXT | Appended by Quantum.Jobs v2
Role context:
This engineering role exists to evaluate, simulate, and benchmark advanced system memory architectures before physical implementation. Situated within the product and system engineering workflow, the position acts as an architectural bridge between memory design specialists and broader system hardware teams. Engineers in this function build high-level virtual simulation models, integrate them onto hardware emulation platforms, and execute performance benchmarks. By analyzing latency, throughput, and bandwidth trade-offs, professionals in this role validate novel hardware concepts, enabling technical organizations to optimize next-generation computing systems.
Quantum ecosystem relevance:
While primarily focused on advanced semiconductor memory architectures for high-performance computing, system modeling engineers contribute indirectly to the broader quantum and classical hybrid infrastructure. Next-generation quantum control systems, error-correction pipelines, and classical-quantum co-processors rely on optimized memory hierarchies to manage high-throughput data streams and reduce bandwidth bottlenecks. By developing robust simulation models and evaluating low-latency memory architectures on hardware emulation platforms, professionals in this engineering function support the foundational computing hardware required to interface with complex computational acceleration environments.
Capability signals:
- Expertise in SystemC software modeling for complex system memory architectures
- Experience deploying hardware emulation platforms to validate system-level performance models
- Ability to conduct architectural benchmarking against baseline memory designs for workload optimization
- Knowledge of computer memory hierarchies including cache, SRAM, and high-bandwidth memory
- Proficiency in C, C++, and Python for architectural modeling and scripting workflows