Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams.
We are seeking passionate FPGA/RTL Design Engineers to help us build a cutting-edge control stack for industrial scale quantum computers.
The stack Qblox develops is a distributed architecture that allows parallel qubit readout, control, intercommunication and other functions, ultimately interacting with the physical qubits using high frequency analog signals. Imagine what it takes to talk to 1000 qubits, with nanosecond-level synchronization and all-to-all connectivity and will understand the design and verification challenges that we face.
We foster a culture of collaboration where every voice is heard and valued. You will have the opportunity to take ownership of your projects, influence technical decisions at higher levels and gain a broad understanding of what goes into our products. You will likely be working in cross-functional teams including electrical engineers, digital design engineers, application engineers and scientists and also have a chance to learn about the Quantum field from our in-house experts.
Your role:
- Understand/evaluate requirements, help design solutions and implement them in VHDL
- Comfortable reading internal and vendor (FPGA, third party ASICs/software) documentation
- Write self-checking testbenches at the module level and occasionally help expand toplevel UVM testbenches
- You will have the opportunity to propose changes to architecture and team processes
- Be a sparring partner to a diverse team of FPGA and embedded software engineers
- We’re constantly trying to find better ways of doing things - be pro-active with proposing your ideas or relevant new developments from the ASIC/FPGA field
Enough about us, what about you?
To really enjoy this role, we imagine that you will possess the following experience:
- A driven FPGA Design engineer that has been working in a similar role and R&D environment for 5+ years.
- Good communication
- Working knowledge of either Xilinx Vivado or Intel FPGA Quartus
- VHDL
- Module-level verification
- High-end simulator tools (e.g. Mentor Graphics QuestaSim)
- Processor and bus-system architecture (e.g. AMBA AXI, Avalon, etc)
- Some scripting ability (python, tcl/tk, shell)
- Git
Optional nice-to-haves:
- Xilinx Zynq-7000 / Ultrascale+/ RFSoC
- (System)Verilog
- Verification frameworks (preferably UVM, but also OVM, OSVVM, Cocotb, etc)
- Timing closure methods
- Linux kernel module development
- DSP
- C/C++
- Microarchitecture design
- Experience in the Quantum field
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
This engineering function is structurally essential for translating theoretical quantum circuit designs into high-throughput, low-latency physical control systems. The ability to manage real-time synchronization across hundreds or thousands of physical qubits is a fundamental prerequisite for advancing the Technical Readiness Level (TRL) of industrial-scale quantum processors. FPGA expertise anchors the hardware-software interface, mitigating the acute latency and scalability bottlenecks inherent in complex control stacks. This role directly influences the industry's capacity to achieve fault-tolerance targets and accelerate the performance validation cycle for quantum computing architectures.-----The FPGA Design Engineer role is positioned within the critical systems layer of the quantum value chain, specifically enabling the interface between high-level classical software and the cryogenic quantum processing unit (QPU). The current macro constraint across the quantum hardware landscape is the "scaling bottleneck," where increasing qubit count far outpaces the corresponding development of scalable, integrated control electronics capable of managing complex pulse sequences, readout, and error correction in real-time. This structural dependency highlights the necessity of highly parallel, deterministic digital signal processing, which FPGAs are uniquely suited to provide.
The industry is rapidly shifting toward distributed, modular control architectures to manage the complexity of larger quantum systems. This evolution requires engineers capable of designing highly synchronous interconnects and processing elements that function reliably at nanosecond precision, a demand that traditional classical HPC architectures struggle to meet. Furthermore, this role contributes directly to addressing vendor fragmentation by building standardized, high-performance control interfaces that can abstract underlying hardware specifics for application developers. The successful deployment of these systems facilitates the shift from research prototypes toward commercial, integrated quantum infrastructure.
Sector-wide efforts continue to address talent and integration challenges in quantum systems. The core innovation leverage for control electronics lies in developing resource-efficient RTL that maximizes the limited resources on commercial-off-the-shelf FPGAs, pushing the envelope on I/O density and signal fidelity necessary for high-fidelity qubit operation. This specialized engineering niche is key to de-risking the industrial transition of laboratory-scale quantum technologies by embedding robustness and performance into the foundational control fabric.-----The core capability domain is the development and verification of Register Transfer Level (RTL) designs optimized for high-speed, parallelized data flow, crucial for managing simultaneous control pulses and readout operations across large qubit arrays. This requires expertise in digital backplane architecture, specifically utilizing high-bandwidth interfaces like AMBA AXI for low-latency communication between processing elements and memory. Verification is architecturally critical, focusing on exhaustive testbench development, often leveraging advanced methodologies like Universal Verification Methodology (UVM), to ensure deterministic, clock-cycle-accurate operation in deployment. Tooling layers include specialized FPGA synthesis and place-and-route environments (e.g., Xilinx Vivado or Intel Quartus) coupled with hardware description languages such as VHDL or SystemVerilog. These capabilities ensure the control system maintains synchronization integrity and minimizes timing jitter, which is paramount for maintaining qubit coherence and fidelity across the operational lifecycle of a QPU.----- * Accelerates the scaling curve for next-generation quantum processor control hardware.
* Enables the requisite timing precision for high-fidelity quantum gate operations.
* Mitigates system latency inherent in distributed qubit control stack architectures.
* Increases the density and parallelism of high-frequency analog signal generation and acquisition.
* Fosters the development of deterministic control pathways essential for error correction protocols.
* Reduces the integration friction between classical control systems and the quantum core.
* Improves the throughput capacity for quantum state readout and initialization cycles.
* Establishes robust verification processes for mission-critical real-time quantum control.
* Drives standardization in the digital hardware interfaces across heterogeneous quantum systems.
* Optimizes resource utilization within commercial Field-Programmable Gate Arrays platforms.
* Supports the migration of computationally intensive signal processing into the dedicated hardware layer.
* Enhances overall system stability required for extended quantum computation runtimes.Industry Tags: Quantum Control Systems, FPGA Development, Qubit Control Hardware, Real-Time Digital Design, RTL Verification, Microwave Engineering, Distributed Architecture, Hardware-Software Interface, Quantum Error Correction, Qblox
Keywords:
NAVIGATIONAL: Field-Programmable Gate Array control stack engineer, Qblox quantum computing jobs, high-speed digital design quantum, real-time qubit control systems, distributed quantum architecture engineering, hardware design engineer VHDL, industrial scale quantum computer control
TRANSACTIONAL: Apply senior FPGA design engineer quantum, career opportunity RTL verification UVM, specialized quantum control hardware development role, Xilinx Vivado digital design position, next-generation qubit interface engineering jobs, quantum control electronics career path, Mentor Graphics QuestaSim verification roles
INFORMATIONAL: Scalability challenges quantum control hardware FPGAs, high-fidelity qubit manipulation techniques control, nanosecond synchronization requirements quantum systems, future of quantum processor control engineering, technical readiness level quantum computing hardware, RTL design for distributed quantum systems, processor bus architecture quantum interface
COMMERCIAL INVESTIGATION: Evaluating commercial quantum control stack vendors, competitive analysis FPGA quantum hardware providers, optimizing parallel qubit readout architectures, supply chain dependencies quantum control electronics, digital hardware solutions for quantum technology, industrial quantum computing infrastructure components
Authority Tag: QED-C and McKinsey Global Institute reports on quantum workforce gaps and hardware scaling.
