Planckianis developing the core technology to power utility-scale quantum computers.
By design, our chip architecture decouples control lines from qubit count, removing a key bottleneck in scaling. It combines the proven reliability of superconducting circuits with a breakthrough approach to qubit control, paving the way for quantum computers capable of solving the world’s most challenging problems.
We are seeking aQuantum Design Engineerto support the design and optimization of superconducting qubits and quantum circuit architectures.
What You'll be doing
- Design superconducting qubits, couplers, and quantum circuits for scalable quantum processors
- Develop and optimize qubit architectures with respect to coherence, frequency crowding, control, and readout
- Perform electromagnetic and circuit-level simulations (participation ratios, loss channels, mode analysis)
- Analyze sensitivity to fabrication tolerances and process variations
- Define design rules that balance performance with manufacturability and yield
- Support the experimental team by interpreting measurement data and feeding results back into design iterations
- Contribute to system-level architectural choices (connectivity, coupling schemes, control simplification)
- Document designs, simulations, and design rationale for internal and external use
Requirements
- PhD or MSc in Physics, Applied Physics, Electrical Engineering, or related field
- Proficiency with EM and circuit simulation tools (e.g., HFSS, Sonnet, COMSOL, or equivalent)
- Background in superconducting qubit physics and circuit quantum electrodynamics (cQED)
- Solid understanding of decoherence mechanisms and materials loss in superconducting devices
- Hands-on experience designing superconducting quantum circuits
- Ability to connect theoretical models with experimental constraints
Every job has its challenges, and this one is no exception. While many companies gloss over them, we believe in being upfront:
- You’ll face tough situations, especially the classic challenge: people problems. Navigating human dynamics can be tricky and requires patience and empathy.
- Some work is unglamorous, but building a great company means rolling up your sleeves. From strategic decisions to hands-on grunt work, everyone contributes to the heavy lifting.
We're not looking for perfection; we're looking for people who are ready to grow through the hard parts and help us build something that lasts.
What We Offer
- Competitive salary + benefits
- Stock options
- Flexible working hours with hybrid working
- Ego-free, merit-based environment
Planckian is an equal-opportunity employer.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The emergence of utility-scale superconducting quantum processors requires a transition from laboratory-scale proof-of-concept devices to industrial-grade architectures. In this context, the role of a Quantum Design Engineer serves as a critical structural bridge between theoretical qubit physics and scalable hardware manufacturing. As the sector moves from the NISQ era toward fault-tolerant systems, this role ensures that individual component fidelities are maintained within the constraints of increasing system complexity. This technical interface is necessary to address the high-fidelity control and wiring bottlenecks currently limiting the physical qubit counts of superconducting platforms. By optimizing the physical layout and electromagnetic properties of quantum circuits, these engineers enable the transition of deep-tech research into reliable, reproducible commercial hardware infrastructure.
The superconducting quantum hardware sector is currently navigating a critical pivot from increasing raw physical qubit counts to achieving the high-fidelity logical qubits necessary for error correction. Within the quantum value chain, design engineering occupies a central position in the "systems and hardware" layer, directly influencing the Technology Readiness Level (TRL) of the entire stack. Macro-level analysis suggests that the primary bottleneck in this layer is no longer the lack of theoretical gate designs, but rather the engineering challenge of managing frequency crowding, cross-talk, and signal integrity as processors scale beyond the hundred-qubit threshold.
Current industry focus lies on bridging classical and quantum capabilities at scale, which necessitates a more integrated approach to chip architecture. While semiconductor fabrication techniques provide a pathway for volume production, the sensitivity of superconducting circuits to sub-nanometer variations in insulator thickness requires a specialized design tier that can model and mitigate fabrication-induced frequency shifts. This variability remains a significant risk to the scalability of multi-junction architectures, often leading to reduced yields or complex post-fabrication calibration requirements.
Furthermore, the integration of cryogenic electronics and multi-layer wiring schemes introduces new thermal and electromagnetic constraints that must be addressed at the design stage. As the ecosystem matures, the ability to co-design qubits with their control and readout circuitry is becoming a strategic differentiator. This holistic architectural approach is essential for reducing the quadratic scaling of wiring overhead and ensuring that the physical footprint of the cooling infrastructure does not become an insurmountable barrier to reaching the thousands of qubits required for practical quantum advantage.
The capability architecture for this role centers on the intersection of microwave engineering, circuit quantum electrodynamics (cQED), and computational electromagnetics. Proficiency in high-frequency simulation environments is required to model the participation ratios and loss channels that govern qubit coherence and gate fidelity. These capabilities are critical for translating abstract quantum algorithms into physical circuit topologies that minimize decoherence mechanisms, such as dielectric loss and flux noise.
Beyond component-level design, this role facilitates a cross-functional coupling between fabrication teams and experimental physicists. By establishing rigorous design rules that account for process variations and material interfaces, engineers ensure the structural throughput of hardware development. This architectural enablement is necessary for the stability of superconducting quantum processors, as it allows for the deterministic optimization of connectivity and coupling schemes. Ultimately, these technical proficiencies provide the leverage needed to synchronize hardware performance with the requirements of evolving quantum software stacks and compiler infrastructures.
Accelerates the transition from experimental prototypes to standardized, scalable quantum hardware architectures
Mitigates systemic risks associated with frequency crowding and crosstalk in high-density superconducting processors
Enhances the operational reliability of quantum processing units through rigorous electromagnetic modeling and simulation
Facilitates the realization of fault-tolerant systems by optimizing physical qubits for logical error correction codes
Reduces the iteration friction between hardware design and cleanroom fabrication cycles through precise tolerance analysis
Strengthens the technological readiness of superconducting platforms for integration into hybrid cloud environments
Optimizes the connectivity and coupling schemes required for complex, multi-qubit gate operations and entanglement
Drives the development of multi-layer wiring solutions to overcome the physical bottlenecks of cryogenic signal delivery
Improves the manufacturing yield of quantum chips by designing for robustness against fabrication-induced variations
Standardizes the documentation and design rationale needed for cross-institutional research and development collaboration
Protects capital-intensive hardware investments by ensuring architectural compatibility with future control electronics
Enables the benchmarking of qubit performance against industry-standard metrics for coherence and gate fidelity
Industry Tags: Superconducting Quantum Computing, Quantum Chip Architecture, Circuit QED, Microwave Engineering, Electromagnetic Simulation, Qubit Scaling, Hardware Integration, Deep Tech Manufacturing, Cryogenic Electronics
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