Planckianis developing the core technology to power utility-scale quantum computers.
By design, our chip architecture decouples control lines from qubit count, removing a key bottleneck in scaling. It combines the proven reliability of superconducting circuits with a breakthrough approach to qubit control, paving the way for quantum computers capable of solving the world’s most challenging problems.
We are seeking aQuantum Design Engineerto support the design and optimization of superconducting qubits and quantum circuit architectures.
What You'll be doing
- Design superconducting qubits, couplers, and quantum circuits for scalable quantum processors
- Develop and optimize qubit architectures with respect to coherence, frequency crowding, control, and readout
- Perform electromagnetic and circuit-level simulations (participation ratios, loss channels, mode analysis)
- Analyze sensitivity to fabrication tolerances and process variations
- Define design rules that balance performance with manufacturability and yield
- Support the experimental team by interpreting measurement data and feeding results back into design iterations
- Contribute to system-level architectural choices (connectivity, coupling schemes, control simplification)
- Document designs, simulations, and design rationale for internal and external use
Requirements
- PhD or MSc in Physics, Applied Physics, Electrical Engineering, or related field
- Proficiency with EM and circuit simulation tools (e.g., HFSS, Sonnet, COMSOL, or equivalent)
- Background in superconducting qubit physics and circuit quantum electrodynamics (cQED)
- Solid understanding of decoherence mechanisms and materials loss in superconducting devices
- Hands-on experience designing superconducting quantum circuits
- Ability to connect theoretical models with experimental constraints
Every job has its challenges, and this one is no exception. While many companies gloss over them, we believe in being upfront:
- You’ll face tough situations, especially the classic challenge: people problems. Navigating human dynamics can be tricky and requires patience and empathy.
- Some work is unglamorous, but building a great company means rolling up your sleeves. From strategic decisions to hands-on grunt work, everyone contributes to the heavy lifting.
We're not looking for perfection; we're looking for people who are ready to grow through the hard parts and help us build something that lasts.
What We Offer
- Competitive salary + benefits
- Stock options
- Flexible working hours with hybrid working
- Ego-free, merit-based environment
Planckian is an equal-opportunity employer.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The structural maturation of quantum hardware necessitates a specialized tier of engineering focused on the deterministic scaling of superconducting qubit architectures. This role type exists to address the critical transition from laboratory-scale prototypes to utility-scale processors by harmonizing high-fidelity electromagnetic design with industrial manufacturability. By optimizing the physical layer of the quantum stack, these experts directly influence the reliability and coherence metrics required for fault-tolerant computing. This function serves as a primary bridge between theoretical circuit quantum electrodynamics and the empirical constraints of large-scale cryogenic systems. As global competition for quantum advantage intensifies, the ability to architect decoupled control systems and scalable interconnects has become a fundamental determinant of systemic throughput.
The superconducting quantum computing sector is currently transitioning from the era of Noisy Intermediate-Scale Quantum devices toward verifiable fault tolerance. A central challenge in this evolution is the "wiring bottleneck," where the complexity of control infrastructure often scales faster than the qubit count itself. Addressing this requires a departure from traditional brute-force scaling in favor of sophisticated architectural innovations that decouple control lines and mitigate frequency crowding. Within this hardware-centric value chain, the role of a Quantum Design Engineer is positioned at the intersection of nanofabrication, microwave engineering, and quantum physics, serving as the technical engine for achieving the gate fidelities necessary for error correction.
Macro-level analysis indicates that while significant public and private capital has flowed into quantum hardware, the industry faces a structural talent shortage in "quantum-aware" engineering. Unlike pure physics research, this discipline demands an understanding of how fabrication tolerances, material loss, and decoherence mechanisms interact at the system level. Furthermore, as the ecosystem moves toward modular and hybrid classical-quantum infrastructures, the standardization of design rules and simulation workflows becomes a national strategic imperative. This shift favors organizations that can integrate advanced electromagnetic modeling with automated design toolchains, thereby reducing the high cost of iterative fabrication cycles and accelerating the progression of Technology Readiness Levels.
The capability architecture for this role type centers on the synthesis of circuit quantum electrodynamics and computational electromagnetics to ensure the structural integrity of quantum processors. Expertise in finite-element analysis and circuit-level modeling allows for the precise characterization of participation ratios and loss channels, which are vital for maintaining long-lived coherence in complex multi-qubit environments. These capabilities are critical for throughput because they enable the predictive optimization of couplers and readout resonators before physical deployment. By establishing a rigorous feedback loop between simulation results and experimental measurement data, these experts facilitate a level of interoperability between theoretical Hamiltonian models and the physical constraints of the dilution refrigerator environment. This technical coupling ensures that system-level architectural choices remain grounded in realistic manufacturability and yield benchmarks.
Accelerates the deterministic progression of superconducting hardware toward fault-tolerant operation regimes
Mitigates systemic scaling risks by implementing architectural solutions for control line decoupling
Enhances the structural throughput of quantum research through high-fidelity electromagnetic simulation workflows
Reduces capital expenditure associated with fabrication iterations by improving predictive design accuracy
Strengthens the long-term reliability of quantum processors through advanced decoherence mitigation strategies
Facilitates the transition from isolated qubit experiments to integrated, large-scale circuit architectures
Optimizes the lifecycle of hardware development by aligning design rules with industrial yield requirements
Supports the scaling of quantum adoption by improving the stability and fidelity of the hardware layer
Shortens the time-to-market for utility-scale systems by resolving critical bottlenecks in qubit connectivity
Improves the reproducibility of quantum hardware performance through rigorous sensitivity analysis of fabrication tolerances
Protects deep-tech investments by providing expert technical validation of scalable processor designs
Enables the strategic orchestration of hardware roadmaps within the broader high-performance computing ecosystem
Industry Tags: Superconducting Qubits, Circuit QED, Quantum Hardware Scaling, Microwave Engineering, Nanofabrication, Cryogenic Systems, Electromagnetic Simulation, Quantum Processor Architecture, Fault Tolerant Computing
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