We are seeking a highly qualified Chief Ion Trap Wafer Fabrication Scientist in Plymouth, MN; Broomfield, CO; or Malta, NY.
In this role you will work closely with a team of physicists, engineers, and technicians, as well as with our foundry partners, to drive forward all aspects of fabrication for our next generation of ion traps and related components, and to develop new and improved methods for producing higher performing and higher quality traps. This influential position will balance technical leadership, individual technical contribution, and external vendor partnership. A successful candidate will have a broad and deep understanding of wafer fabrication in both IC and MEMS environments, as well as a proven track record of advancing R&D efforts beyond the state of the art. Quantinuum believes that employees work better, more efficiently and more collaboratively in close proximity to other employees, where ideas can be exchanged readily, and decisions can be made more quickly for the benefit of the Company and our customers. All employees should work at their assigned location; however, this role may offer the opportunity to work remotely up to 2 days per week, with approval.
All applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.
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Key Responsibilities:
- The ability to lead and drive all stages of development of microfabricated ion traps, including new concept creation, design, layout, fabrication, packaging and characterization
- Contribute to strategic, long-range planning
- Work closely with an integrated team of scientists, engineers and technicians to translate system requirements and designs into functional hardware
- Engage with 3rd parties to cultivate possible key partnerships, supplier relationships, and co-development opportunities
YOU MUST HAVE:
- Bachelor’s degree minimum
- Minimum 15+ years' experience in one or more of the following areas: Semiconductor/MEMS process development, Ion trap design and fabrication, integrated optics of waveguides, and chip-scale photonics (PhD/Masters inclusive)
- Due to U.S. export control laws, must be a US citizen (Plymouth, MN only)
- Due to Contractual requirements, must be a U.S. Person defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status.
- Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.
WE VALUE:
- PhD in Physics or Engineering preferred
- Relevant work experience in a micro-fabrication process environment
- Experience with a wide range of semiconductor/MEMS processes and processing tools including layout, deep reactive ion etching, photolithography, e-beam lithography, thin film deposition and electroplating
- 10+ years’ experience working with external foundries strongly preferred
- Knowledge of on-chip silicon photonics, photonic modeling and fiber-to-chip coupling
- Experience with Finite Element Modeling (mechanical, thermal, electrical, magnetic, optical and multi-physics) of MEMS-like structures
- Experience with 2.5/3D packaging; Experience with optical/semiconductor packaging
- Experience working in an R&D environment
- Published results within their field of research
- Patented results within their field of research
- Experience working within a cross-functional team environment
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$208,000 - $260,000 a year
Compensation & Benefits:
Incentive Eligible – Range posted is inclusive of bonus target
The pay range for this role is $208,000 – $260,000 annually. Actual compensation within this range may vary based on the candidate’s skills, educational background, professional experience, and unique qualifications for the role.
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TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The transition of trapped-ion quantum computing from laboratory environments to industrial-scale manufacturing represents a pivotal shift in the global deep-tech value chain. This role type is structurally necessary to bridge the gap between experimental physics and high-volume semiconductor fabrication, ensuring that next-generation quantum processing units achieve the fidelity and reproducibility required for fault-tolerant operations. By synchronizing micro-electro-mechanical systems (MEMS) innovation with commercial foundry protocols, this function mitigates the systemic risk of architectural obsolescence. Market signals from the Quantum Economic Development Consortium indicate that such specialized leadership is essential for securing the stability of hardware supply chains. This strategic position converts advanced research into deterministic technology roadmaps, providing the necessary leverage to scale quantum infrastructures for global enterprise adoption.
The quantum hardware sector is currently navigating a decisive transition toward Technology Readiness Level (TRL) maturity, where the primary bottleneck has shifted from fundamental feasibility to scalable integration. Within the trapped-ion modality, the complexity of managing wafer-level fabrication across diverse foundry environments creates a significant structural dependency. As organizations move beyond NISQ-era benchmarks, the ecosystem requires specialized architects capable of orchestrating the convergence of CMOS-compatible processes with specialized ion-trap requirements, such as cryogenic compatibility and integrated photonics.
Workforce scarcity is particularly acute at the intersection of traditional semiconductor manufacturing and quantum information science. National technology strategies highlight that the ability to maintain domestic manufacturing advantages depends on senior researchers who can navigate complex export control frameworks and international intellectual property landscapes. The current sector-wide focus lies on bridging classical and quantum capabilities at scale, necessitating a sophisticated management of the software-hardware interface to ensure that fabricated components meet the rigorous throughput requirements of production environments.
Furthermore, the evolution of the value chain depends on the ability to translate material science breakthroughs into functional hardware without disrupting established supply chain logistics. Consequently, the availability of senior leadership capable of managing external vendor partnerships is a primary determinant of whether a commercial organization can successfully transition from exploration to deployment. This structural layer of expertise is the primary mechanism for maintaining momentum as the technology faces increasing pressure for commercial viability.
The capability architecture for this role type centers on the synchronization of advanced wafer fabrication protocols with the specific constraints of quantum system engineering. Mastery of the interface between integrated circuit (IC) design and MEMS processing is essential for ensuring that ion traps are optimized for surface-noise reduction and high-gate-fidelity operations. This requires a deep understanding of the integration points between thin-film deposition, deep reactive ion etching, and fiber-to-chip coupling. These capabilities are fundamental to the throughput of technology organizations, as they enable the parallelization of hardware research alongside the development of scalable packaging solutions. By establishing rigorous verification and validation frameworks, this function provides the leverage needed to assess the long-term reliability of quantum processors. Furthermore, the ability to manage complex cross-functional dependencies ensures that scientific outputs are reconciled with the practical constraints of foundry-scale yield and reproducibility. Such expertise reduces the iteration friction between abstract research and hardware delivery, which is critical for long-term interoperability within the emerging quantum-as-a-service market. - Accelerates the deterministic transition from laboratory-scale trapped-ion research to industrial-grade hardware manufacturing
- Mitigates systemic execution risks by synchronizing long-term fabrication research with near-term technology roadmaps
- Facilitates the integration of advanced photonic components into standardized semiconductor and MEMS fabrication workflows
- Strengthens the reliability of hardware technology strategies through the implementation of rigorous wafer-level benchmarking
- Reduces iteration friction between fundamental material science breakthroughs and the deployment of scalable quantum architectures
- Optimizes the allocation of specialized technical talent across design, layout, and foundry-scale manufacturing portfolios
- Enhances the stability of the quantum hardware value chain by providing predictable requirement frameworks for foundry partners
- Supports the scaling of system performance by managing the complex dependencies of 2.5D and 3D packaging technologies
- Improves the transparency of hardware readiness level progression for stakeholders in the investment and policy sectors
- Enables the structural reproducibility of quantum experiments through the standardization of fabrication implementation protocols
- Protects high-capital research and development investments by ensuring alignment between scientific discovery and commercial scalability
- Orchestrates the convergence of academic research pathways with the practical demands of global semiconductor manufacturing networksIndustry Tags: Trapped-Ion Fabrication, MEMS Engineering, Semiconductor Process Development, Quantum Hardware Scaling, Integrated Photonics, Wafer Scale Manufacturing, Deep Tech Strategy, TRL Progression, Foundry Management
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