About The Role and Team
Quantum Motion is a fast-growing quantum computing scale-up based in London founded by internationally renowned researchers from UCL and Oxford University with over 40 years’ experience in developing qubits and quantum computing architectures. Bringing together state-of-the-art cryogenic facilities and an outstanding interdisciplinary team, we are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more.
Our Team
Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times in 2021 and 2022, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million.
We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.
This is a rare and exciting opportunity to be an employee at a scale-up shaping the future of quantum computing. There are vast opportunities for professional growth and to make an impact within the company.
Our team of 100+ is based across London, Oxford, San Sebastián and Sydney, with our primary hub in Islington (London).
Functions of the Role
We’re looking for a visionary and hands-on 3D Integration and Advanced Packaging lead to bridge the gap between cutting-edge silicon spin qubit devices and scalable quantum systems.
In this role, you will build and lead a team to drive the R&D of complex, multi-chip modules utilising TSVs and microbumps, optimised to operate at millikelvin temperatures. This is a rare and exciting opportunity to solve the industry’s toughest interconnect bottlenecks and shape the physical architecture of next-generation quantum processors.
- Recruit, mentor, and lead a high-performing team of packaging, signal integrity, materials, and quantum integration engineers.
- Drive the strategy, design, and rapid prototyping of 3D integrated circuits and multi-chip quantum modules.
- Ensure all packaging architectures and interconnects can withstand thermal cycling down to millikelvin regimes without delamination or performance degradation.
- Own relevant operations with external foundries, OSATs, and research partners. Seamlessly transfer novel packaging designs to external manufacturing lines.
- Serve as the critical link between design, process integration, cryo R&D, and quantum hardware teams to co-optimise the electrical, thermal, and mechanical design.
- Balance rapid R&D prototyping with a rigorous, parallel focus on yield improvement, failure analysis, and long-term reliability.
Experience - Essentials
- Master’s or PhD in electrical engineering, materials science, physics, microelectronics, or related field.
- 7+ years deep technical experience in 3D integration, specifically with TSVs, fine-pitch microbumps, flip-chip bonding, and/or multi-chip modules.
- Proven track record or building, scaling, and managing engineering teams in high-tech, fast-paced environments.
- Strong experience managing technical transfers and working closely with external semiconductor foundries or advanced packaging facilities.
Experience - Desirable
- Proficiency with industry-standard simulation tools (e.g., Ansys HFSS/Q3D, Cadence) to model signal integrity, thermal stress, and mechanical behaviour.
- Direct experience with cryogenic electronics.
- Background or strong familiarity with solid-state quantum mechanics, silicon spin qubits, or semiconductor physics.
- Knowledge of materials behaviour (superconductors, low loss dielectrics) at extreme temperatures.
Benefits
- Be part of a creative, world-leading team
- Competitive salary and share options scheme
- Contributory pension scheme
- Group private medical insurance scheme
- Life Assurance
- Cycle-to-work Scheme
- Central London location
EEO Statement
Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The shift from laboratory-scale experiments to industrial-grade quantum computing is increasingly defined by the transition from discrete component assembly to monolithic and 3D heterogeneous integration. As qubit counts scale, the "interconnect bottleneck" emerges as a primary systemic risk, where the density of classical control wiring threatens the thermal and physical integrity of cryogenic environments. Expertise in 3D integration and advanced packaging is therefore a structural necessity for the ecosystem, serving as the bridge between fundamental qubit discovery and the delivery of fault-tolerant, scalable architectures. This role type secures the physical viability of the quantum value chain by ensuring that increasing architectural complexity does not compromise system reliability or manufacturability. By stabilizing the hardware-control interface at millikelvin scales, this function transforms theoretical scalability into a deterministic engineering roadmap, mitigating the risks of technology stagnation during the transition to large-scale deployment.
The global quantum hardware landscape is currently navigating a pivotal transition from Technology Readiness Level (TRL) 4 to TRL 7, where the primary challenge is no longer just qubit coherence, but the physical orchestration of thousands of interconnected qubits. While various modalities exist, silicon-based spin qubits benefit significantly from leveraging existing CMOS manufacturing ecosystems, yet they face unique packaging constraints due to extreme cryogenic operating conditions. The industry is witnessing a decisive move toward 3D integrated circuits (3D-ICs) to minimize signal latency and cable-induced heat loads, which are critical for maintaining the fragile quantum states required for fault tolerance.
Workforce scarcity in this domain is acute, as it requires a rare convergence of semiconductor packaging expertise and deep knowledge of cryogenic physics. Current sector-wide efforts continue to address talent and integration challenges in quantum systems, particularly regarding the reliability of through-silicon vias (TSVs) and micro-bumps under repetitive thermal cycling. As public funding and private investment flow into national quantum hubs, the availability of specialized engineering leadership becomes a primary determinant of whether a scale-up can successfully transition designs from research labs to high-volume commercial foundries.
Furthermore, the ecosystem faces a growing need for standardization in the packaging layer to support interoperability and supply chain resilience. The integration of high-density interconnects must be balanced against the parasitic effects of packaging materials on qubit performance, such as dielectric loss and microwave interference. Consequently, this strategic layer of engineering is essential for managing the complex dependencies between chip design, process integration, and external OSAT (Outsourced Semiconductor Assembly and Test) partnerships, ensuring that the next generation of quantum processors can move beyond proof-of-concept into reliable, mass-producible systems.
The capability architecture for this role type centers on the synchronization of advanced semiconductor packaging protocols with the stringent requirements of quantum information science. Mastery of 3D integration techniques, including fine-pitch flip-chip bonding and TSV implementation, is essential for reducing the physical footprint of control electronics. This expertise is fundamental to system throughput, as it enables higher interconnect density while managing the electro-thermal coupling that occurs during rapid signal switching. Furthermore, the ability to model mechanical stress and signal integrity within multi-chip modules ensures that disparate materials—from superconductors to low-loss dielectrics—maintain structural integrity across extreme temperature gradients. These technical pillars provide the leverage needed to stabilize the hardware stack, reducing the iteration friction between chip design and system deployment. By establishing rigorous verification frameworks for packaging reliability, this function ensures that quantum hardware can scale without the systemic failures associated with thermal delamination or signal degradation. Such capabilities are critical for maintaining interoperability within a fragmented vendor landscape and for securing the long-term stability of the hardware-to-software interface. - Accelerates the transition from laboratory prototypes to scalable, manufacturable quantum processor architectures
- Mitigates systemic hardware failure risks through the validation of cryogenic-grade 3D interconnect reliability
- Facilitates the integration of high-density classical control circuitry with sensitive quantum bit arrays
- Strengthens the reliability of the quantum supply chain by bridging internal R\&D and external foundry processes
- Reduces iteration cycles in hardware development by co-optimizing thermal, electrical, and mechanical design parameters
- Optimizes the physical footprint of quantum systems to meet the cooling power constraints of existing dilution refrigerators
- Enhances the throughput of quantum hardware teams by resolving critical interconnect bottlenecks at scale
- Supports the achievement of fault-tolerant benchmarks through the reduction of signal latency and noise interference
- Improves the transparency of technology readiness progression for stakeholders in the investment and policy sectors
- Enables the structural reproducibility of quantum system assembly via standardized advanced packaging protocols
- Protects high-capital R\&D investments by ensuring alignment between qubit breakthroughs and commercial scalability
- Orchestrates the convergence of traditional semiconductor manufacturing workflows with the demands of deep-tech innovationIndustry Tags: 3D Integration, Advanced Packaging, Silicon Spin Qubits, Cryogenic Engineering, TSV Technology, Heterogeneous Integration, Quantum Hardware Scaling, Microelectronics, System-on-Chip
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