We are seeking a Layout Automation Engineering Intern in our Brooklyn Park, MN location.
This internship will explore solutions that will help us automate and accelerate our physical layout of ion traps and related chips. This position will perform a capability assessment and work with the team to develop test cases to demonstrate new capabilities as well as identify gaps where solutions are needed.
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Key Responsibilities:
- Explore Layout automation tools and workflows that can potentially speed up our ion trap layout process. Perform a trade study and develop use cases to demonstrate improvements.
- Work with the layout team to Develop Python and SKILL based automation tools and verify their effectiveness for ion trap layout
- Help with smaller, R&D layout projects whenever possible, and become familiar with our design through tapeout process
YOU MUST HAVE:
- Currently enrolled and pursuing undergraduate or graduate degree with graduation date on/after 2027
- Due to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status
- Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.
WE VALUE:
- 3+ years computer programming experience in Python, C/C++, Cadence SKILL scripting, TCL/TK or other programming languages strongly preferred
- Exposure to EDA/CAD-based tools and methodologies preferred
- Currently pursuing a Masters in electrical engineering, physics, mathematics or computer science preferred
- Experience performing semiconductor or MEMS photolithography mask layout using Cadence Cadence Virtuoso, L-Edit, k-layout or Synopsis tools
- Hierarchal physical layout design practices
- Experience in automation, machine learning and generative AI tools for programming and workflow development
- Experience with layout of electronic, photonic and MEMS devices
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$27 - $39 an hour
Compensation & Benefits:
The pay range for this role is $27 - $39 per hour. Actual compensation within this range may vary based on the candidate’s skills, educational background, professional experience, and unique qualifications for the role.
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Quantinuum is a leading quantum computing company delivering a full stack platform designed to make quantum computing deployable in real-world environments. With active engagements spanning pharmaceuticals, material science, financial services, government, industrial sectors, and leading academic and research institutions worldwide, we are helping organizations unlock the transformative potential of quantum computing.
Our global team of more than 800 employees includes many of the world's leading scientists, engineers, and researchers, with more than 70% of our technology team holding advanced degrees at the Master's or PhD level. Headquartered in Broomfield, Colorado, Quantinuum operatesacross the United States, United Kingdom, Germany, Japan, and Singapore.
By joining Quantinuum, you’ll help shape the future of quantum computing, pushing the limits of technology, and making the impossible possible.
What’s in it for you?
We believe our people are our greatest strength and offer a comprehensive rewards package that supports your professional growth, well-being, and long-term success.
- For candidates located outside of this state, this role will include a housing stipend of $500 per check/bi-weekly
- A competitive market rate and innovative, game-changing work
- Flexible work schedule
- Employee discounts
Equal Opportunity Employer
Quantinuum is proud to be an equal opportunity employer. We are committed to building an inclusive workplace where all employees and applicants are treated with respect and provided equal opportunities regardless of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, ancestry, marital status, or any other characteristic protected by applicable law.
Know Your Rights: Workplace discrimination is illegal. For more information about Quantinuum, please visit our website.
We are committed to making our recruitment process accessible to all. If you require any reasonable adjustments at any stage of the application or interview process, please let us know use the Lets talk contact form.
Applications will be accepted on an ongoing basis, there is no application deadline for this position.
QUANTUM ROLE CONTEXT | Appended by Quantum.Jobs v2
Role context:
This role exists to optimize the physical design pipeline for specialized hardware components by introducing automated electronic design workflows. Positioned within the hardware development unit, the function acts as an operational link between software tool developers, chip designers, and foundry integration teams. By creating custom scripts and evaluating automation software, professionals in this capacity help shorten design cycles, minimize manual layout errors, and streamline the transition of complex microfabrication patterns from initial schematics to final physical tapeout specifications.
Quantum ecosystem relevance:
The position contributes to the quantum enabling infrastructure by accelerating the physical design and fabrication readiness of physical quantum chips and trapped-ion architectures. As quantum hardware designs scale in physical complexity, automated layout tools become essential for managing high-density control lines and intricate chip geometries. By developing dedicated design automation routines, this function supports hardware scaling efforts, enabling physical design teams to rapidly prototype, iterate, and manufacture custom quantum microarchitecture components efficiently.
Capability signals:
- Proficiency in electronic design automation scripting and CAD workflow enhancement
- Knowledge of semiconductor and microelectromechanical systems physical layout methodologies
- Ability to evaluate design tools and perform comparative technical trade studies
- Understanding of full-cycle chip layout, verification, and tapeout preparation processes
- Skill in writing automated scripts to streamline hardware layout design cycles
