About Us
Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known trade-offs of semiconductor memory devices, ultimately enabling the future of computing.
We are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and disrupt the industry together.
About What You Will Do
As a Senior Staff Physical Design Engineer, you will take technical leadership in the physical implementation of next-generation high-performance SoCs targeting 16nm FinFET technologies and below.
In this role, you will:
- Lead the full RTL-to-GDSII physical implementation flow, including synthesis, floorplanning, place & route, CTS, timing closure, and sign-off.
- Define and execute implementation strategies optimized for FinFET technologies, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.
- Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to achieve the best PPA (Power, Performance, Area) targets.
- Conduct power integrity analysis and ensure robust IR drop and electromigration (EM) margins.
- Drive physical verification closure including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.
- Collaborate closely with RTL and DFT teams to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.
- Interface with foundries and EDA vendors to address technology-specific implementation challenges.
- Contribute to EDA flow improvements and automation through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.
- Act as a technical pillar and mentor within the physical design team, supporting complex debugging and advanced optimization strategies.
About who you are:
- Master’s in Electrical Engineering or related field.
- 10+ years in full-custom layout for memory and/or analog/mixed-signal IPs.
- Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.
- Proficient in layout tools (Virtuoso, Calibre), proficiency in CAD scripting is considered as a big plus.
- Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is a plus.
- Experience in in-memory computing layout is a plus.
- Self-motivated, self-directed, and well-organized.
- We like to build a high performing dream team and count on your excellent communication and interpersonal skills, and ability to engage effectively with your colleagues, our partners, and stakeholders.
- Good English communication skills, knowledge of French and/or Dutch is considered a bonus.
Why Join Us:
- You will get the opportunity to work at the forefront of memory technology innovation.
- Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
- You can be part of a talented and dedicated team in a fast-paced startup environment.
- In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
- You can count on a motivating total rewards package.
How to show your interest in our vacancy: Does the above sounds like you are ready to join our team, please upload your CV.
Vertical Compute is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Join us in shaping the future of compute & memory technology and celebrating success!
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The emergence of specialized deep-tech architectures for high-performance computing has created a structural demand for senior-level physical design expertise capable of navigating sub-16nm FinFET geometries. As the semiconductor industry transitions toward post-Moore scaling and memory-centric computing, this role serves as the critical technical bridge between architectural innovation and silicon realization. Within the value chain, high-precision physical implementation ensures that theoretical PPA advantages are preserved through the manufacturing process, directly impacting the TRL progression of novel compute substrates. Market signals from major foundry roadmaps and deep-tech investment trends highlight a persistent scarcity of engineers who can synchronize complex RTL-to-GDSII flows with advanced node constraints. Consequently, this function is a primary determinant of hardware reliability and energy efficiency in the next generation of accelerated systems. By securing physical integrity at the layout level, this role enables the translation of deep-tech research into scalable, commercially viable infrastructure.
The global semiconductor ecosystem is currently defined by a divergence between general-purpose logic and specialized "beyond-CMOS" or memory-augmented architectures. Within this landscape, physical design functions occupy a pivotal position in the hardware value chain, acting as the final validation layer before fabrication. The transition to FinFET and gate-all-around structures has introduced a level of complexity where physical effects—such as electromigration, IR drop, and parasitics—no longer function as secondary considerations but as primary architectural constraints. This necessitates a strategic shift from traditional implementation to a deeply integrated, physically aware design methodology.
Macro-level constraints in the deep-tech sector are increasingly dominated by the technical debt associated with scaling emerging memory and in-memory computing technologies. While algorithmic breakthroughs promise orders-of-magnitude improvements in energy efficiency, the structural throughput of the industry is throttled by a shortage of specialized talent capable of merging custom analog/mixed-signal layout with high-density digital flows. This talent gap creates a significant bottleneck in the time-to-market for innovative hardware startups seeking to disrupt established compute-memory trade-offs.
Furthermore, the fragmentation of EDA tooling and the rising cost of advanced foundry access require a more sophisticated approach to implementation strategy. Ecosystem-level initiatives now prioritize "first-time-right" silicon to mitigate the capital-intensive nature of sub-16nm development. As sovereign national strategies increasingly emphasize domestic semiconductor capability and hardware-level security, the role of physical design becomes even more critical. It ensures that specialized deep-tech assets, such as those developed by Vertical Compute, can be seamlessly integrated into broader high-performance computing environments. Ultimately, the maturation of this engineering domain is essential for the transition from experimental semiconductor prototypes to the standardized, high-yield manufacturing required for global infrastructure deployment.
The technical architecture of this role is built upon a dual-core capability in advanced lithographic implementation and multi-domain physical sign-off. Mastery of RTL-to-GDSII flows within FinFET nodes represents the primary mechanism for transforming high-level logic into verifiable silicon structures. These capabilities are not merely operational; they provide the structural stability required for high-performance SoC integration. By optimizing Multi-Mode Multi-Corner timing closure and power integrity, the design function mitigates the systemic risks of post-silicon failure and performance degradation.
This domain further acts as the interface point between architectural research and foundry-specific manufacturing constraints. The application of sophisticated EDA automation and custom CAD scripting provides the leverage needed to scale complex layouts without compromising design quality. This technical-scientific coupling ensures that emerging memory technologies can achieve the density and reliability targets demanded by modern data-intensive applications. Ultimately, these capabilities enable the deterministic scaling of hardware platforms, facilitating interoperability between novel memory substrates and standard digital logic, which is a prerequisite for the broader adoption of next-generation computing architectures. - Standardizes the physical implementation protocols for next-generation deep-tech architectures targeting sub-16nm FinFET nodes
- Mitigates systemic manufacturing risks by ensuring rigorous adherence to advanced design rule checks and physical sign-off standards
- Facilitates the transition from laboratory-scale memory research to production-ready semiconductor intellectual property
- Optimizes the energy-to-performance ratio of high-performance computing systems through advanced power integrity and IR drop analysis
- Strengthens the reliability of sovereign semiconductor supply chains by enabling first-time-right silicon for specialized compute hardware
- Reduces the iteration cycle between architectural concept and tape-out through highly automated and scriptable implementation flows
- Enhances the interoperability of novel memory devices with established system-on-chip frameworks via physically aware integration
- Accelerates the TRL progression of in-memory computing technologies through high-precision analog and mixed-signal layout implementation
- Supports the architectural scaling of accelerated systems by resolving multi-corner timing constraints in complex, high-speed logic
- Improves the commercial viability of deep-tech hardware startups by streamlining the path to high-yield foundry manufacturing
- Harmonizes cross-functional design efforts between digital logic and custom analog blocks to ensure cohesive system-level performance
- Safeguards the underlying value of proprietary hardware innovations by codifying them into enforceable, high-fidelity physical representationsIndustry Tags: Semiconductor Physical Design, FinFET Technology, RTL-to-GDSII Flow, Deep Tech Hardware, In-Memory Computing, SoC Implementation, PPA Optimization, EDA Automation, Advanced Node Engineering, High-Performance Computing
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- INFORMATIONAL: Challenges of 16nm FinFET physical design, Evolution of in-memory computing hardware, Semiconductor industry workforce trends 2026, Impact of IR drop on FinFET performance, Best practices for MMMC timing closure, Future of deep tech memory architectures, Scaling semiconductor startups in the EU
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