About Quandela:
Quandela is a European deeptech scale-up building modular, scalable and energy-efficient photonic and spin-optical quantum computers.
Our quantum computing platform is accessible both via the cloud and on-premises.
With a team of more than 140 people, we develop our own hardware and software stack, from semiconductor quantum emitters and photonic processors to quantum control systems and quantum algorithms.
Our ambition is to build large-scale fault-tolerant quantum computers capable of solving problems beyond the reach of classical computation using Quandel’s cutting-edge quantum dot technology.
Within this roadmap, Quantum Error Correction and Fault-Tolerant Quantum Computing play a central role in transforming photonic quantum processors into scalable and reliable computing platforms.
About this position:
You will join the Fault-Tolerant Quantum Computing team within Quandela’s Architecture division. The team brings together researchers, engineers, and students working on Quantum Error Correction and fault-tolerant protocols.
The team works closely with the quantum information, quantum device physics, software and experimental teams across the company.
Within this framework, you will contribute to the development of quantum error correction and fault-tolerant computing strategies that enable the scaling of Quandela’s Spin-Optical Quantum Computing architecture.
Research topics include quantum error-correcting codes, decoder design, fault-tolerant logical operations, resource estimation, and simulation methods, with the goal of developing the best pathway toward fault tolerance for Quandela’s technology.
What You'll do:
As a Quantum Error Correction Researcher, you will contribute to the development of fault-tolerant strategies supporting Quandela’s roadmap toward scalable quantum computing.
Your work will include:
- Study and evaluate quantum error-correcting codes under realistic noise assumptions.
- Design and benchmark fault-tolerant protocols and logical operations.
- Develop and use simulation tools to assess QEC and FTQC strategies.
- Evaluate decoders and analyze their performance trade-offs.
- Collaborate across teams to connect theory with implementation constraints.
- Contribute to publications, conference talks, and academic collaborations.
- Track and assess advances in Fault-Tolerant Quantum Computing and related fields.
Ideal Profile:
We are looking for a researcher with expertise in QEC and a strong interest in bridging theoretical advances with practical fault-tolerant quantum computing architectures.
- PhD, or near completion of a PhD, in Physics, Mathematics, Computer Science, Quantum Information, or a related field.
- Research experience in Quantum Error Correction, FTQC, or related topics within quantum information science.
- Experience with scientific programming and numerical simulations.
- Experience with decoding, compilation, resource estimation, or QEC codes is a plus.
- Ability to collaborate within multidisciplinary teams.
- Fluent in English (French is not required).
- Curiosity, scientific rigor, and willingness to learn.
Bonus Points
- Track record of scientific publications appropriate to career stage.
- Experience with Stim or similar simulation frameworks.
- Experience working with quantum computing hardware
- Familiarity with photonic QC concepts is appreciated but not required.
- Ability to communicate complex ideas clearly.
- Flexible working environment across our Paris/Massy offices.
- Profit-sharing and a company savings plan
- Public transport subscription covered at 50%
- Annual sustainable mobility bonus for eco-friendly transport (e-bike, electric car)
- Fully covered health insurance (Alan)
- Referral program (€1,000 for a junior and €2,000 for an experienced candidate)
- Access to a nursery via choisir-ma-creche or contribution to childcare expenses
- Subsidy for gym membership and sports activities (Gymlib)
- Meal subsidies (Swile)
Process
- Talent Acquisition Interview (30' - 45')
- Hiring Manager Interview (45')
- Seminar on selected work for the FTQC team
- Meeting with the teams - Situational exercise with the FTQC team
- Three Reference Checks
- Offer
Beyond That:
At Quandela, we value intellectual diversity, curiosity, and initiative. If you're passionate about QEC and see yourself contributing, even if you don't meet every listed requirement, we'd love to hear from you : If you're driven by scientific challenges and inspired by the future of quantum computing, let's talk !
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The transition from Noisy Intermediate-Scale Quantum (NISQ) devices to Fault-Tolerant Quantum Computing (FTQC) represents the primary structural hurdle for the commercialization of quantum technologies. Quantum Error Correction (QEC) research is the critical architectural layer required to mitigate the intrinsic fragility of quantum states and ensure computational reliability at scale. As hardware platforms move toward modularity and high-density integration, the ability to implement robust error suppression becomes the decisive factor in achieving practical quantum advantage. This role type serves as the technical bridge between experimental physics and scalable system architecture, addressing the fundamental reliability gap in the current deep-tech value chain. Market signals indicate that the availability of logical qubits, enabled through advanced QEC protocols, is now the leading indicator for investment readiness in the global quantum ecosystem.
The quantum computing industry is currently navigating a period of rapid technological maturation where the emphasis is shifting from qubit counts to qubit quality and system-level fidelity. Within the hardware and systems layer of the value chain, the implementation of fault tolerance is no longer a peripheral research interest but a core strategic requirement for scaling. Macro-level analysis of national quantum strategies reveals that public and private funding is increasingly concentrated on platforms demonstrating a clear pathway to error-corrected operations. This shift is driven by the recognition that current hardware limitations, characterized by high error rates and decoherence, prevent the execution of complex algorithms required for industrial-scale simulation and optimization.
Talent shortages in the specialized field of quantum information theory and fault-tolerant architecture represent a significant bottleneck for the sector. While academic research continues to yield novel stabilizer codes and topological approaches, a critical gap exists in the translation of these theoretical constructs into hardware-specific implementations. The complexity of integrating error-correcting codes with realistic noise profiles and hardware constraints, such as those found in photonic or superconducting systems, requires a multi-disciplinary approach. Organizations are increasingly adopting co-design methodologies where algorithm development and hardware engineering are synchronized to optimize the performance of early-stage fault-tolerant prototypes.
Furthermore, the diversification of quantum hardware modalities—ranging from neutral atoms and trapped ions to photonics—has led to a fragmented vendor landscape. Each modality presents unique noise characteristics, necessitating tailored QEC strategies and decoder designs. As the industry moves toward interoperability and standardized benchmarks, the focus is pivoting toward establishing verifiable metrics for fault-tolerant performance. This evolution favors the development of modular software toolchains and simulation frameworks that can facilitate the offloading of specific error-correction subtasks, ensuring that technology roadmaps remain grounded in realistic hardware trajectories.
The capability architecture for this role type centers on the integration of quantum information theory with advanced numerical simulation and system modeling. At the foundational layer, mastery of error-correcting codes—specifically those targeting platform-specific noise models—is essential for ensuring the stability of logical qubits. This technical proficiency is coupled with a deep understanding of decoder architecture, where the latency and resource overhead of error processing must be balanced against the requirements of real-time quantum operations. These capabilities are critical for the structural throughput of quantum research, as they directly influence the scalability and reliability of high-fidelity models across diverse hardware platforms.
Beyond purely theoretical formulation, the role facilitates a high-level coupling between abstract protocols and practical architectural constraints. This interface ensures that breakthroughs in fault-tolerant logic are translated into tangible system requirements that can be supported by evolving control stacks and cryostat-level hardware. By standardizing the benchmarking of protocols and the estimation of physical resource requirements, these experts enable a level of operational readiness that allows organizations to navigate the transition toward large-scale quantum processors. This strategic alignment is vital for maintaining the integrity of the technology stack as the ecosystem approaches the threshold of fault-tolerant application-scale computing.
Accelerates the deterministic progression of technology readiness levels for fault-tolerant photonic quantum systems
Mitigates systemic risks associated with hardware-specific noise by developing robust error suppression protocols
Facilitates the transition from noisy intermediate-scale devices to standardized fault-tolerant computing platforms
Reduces the resource overhead required for logical qubit encoding through optimized code design
Strengthens the long-term competitive positioning of deep-tech organizations by securing expertise in fault tolerance
Harmonizes abstract quantum information theory with the practical requirements of scalable hardware architectures
Optimizes the performance of real-time decoders to improve the operational stability of quantum processors
Supports the scaling of quantum adoption by ensuring the reliability of complex algorithmic executions
Shortens the iteration cycles for hardware co-design through high-fidelity simulation of error protocols
Improves the accuracy of resource estimation for large-scale industrial quantum applications
Protects capital-intensive investments in quantum hardware by providing expert validation of fault-tolerant roadmaps
Enables the strategic orchestration of research efforts across global networks of academic and industrial partners
Industry Tags: Quantum Error Correction, Fault Tolerant Quantum Computing, Photonic Quantum Systems, Quantum Information Theory, QEC Codes, Decoder Architecture, Scalable Quantum Hardware, Resource Estimation, Quantum Simulation
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