Alice & Bob is developing the first universal, fault-tolerant quantum computer to solve the world’s hardest problems.
The quantum computer we envision building is based on a new kind of superconducting qubit: the Schrödinger cat qubit 🐈⬛. In comparison to other superconducting platforms, cat qubits have the astonishing ability to implement quantum error correction autonomously!
We're a diverse team of 250+ brilliant minds from over 35 countries united by a single goal: to revolutionise computing with a practical fault-tolerant quantum machine. Are you ready to take on unprecedented challenges and contribute to revolutionising technology? Join us, and let's shape the future of quantum computing together!
About the role
We are seeking a Senior Integration & Yield Engineer to join the Foundries & Process Integration team within the Quantum Hardware & Infrastructure department.
The role sits at the interface between qubit design and the chip manufacturing teams. Its purpose is twofold: ensure that device designs translate reliably into high-performing fabricated circuits, and provide the data foundation for process improvement decisions. You will own yield monitoring across our fabrication flows, lead the analysis of fabrication and test data, and maintain the interfaces between design and manufacturing — supporting the scale-up from tens of qubits to a few hundred, and enabling our path toward fault-tolerant quantum computing.
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Responsabilities
Yield engineering & data analysis
- Own yield monitoring across fabrication flows: define metrics, build automated dashboards (wafer reports), and provide real-time visibility of fab performance and yield.
- Lead root cause analysis of systematic and random yield detractors, in collaboration with the chip manufacturing teams.
- Perform advanced statistical analysis (using Python/JMP) to ensure process stability and control variability.
- Develop strategies to reduce inductance/frequency non-uniformity within and across wafers, improving the consistency of qubit performance (frequency targeting, coherence times).
Process Integration
- Define and maintain robust integration flows of POR (process of reference), ensuring design-to-fab alignment.
- Establish Design for Manufacturability (DFM) guidelines.
- Document and maintain reference fabrication flows, yield dashboards, and process KPIs to support process reviews.
Design-to-fabrication interface
- Own the look-up tables (LUT) linking design parameters to Josephson junction fabrication, and maintain their accuracy as fabrication processes evolve.
- Test and implement Design Rule Manual (DRM) extensions in collaboration with the design and fabrication teams, and establish Design for Manufacturability (DFM) guidelines.
- Translate device designs into fabrication-ready wafer layouts (wafer layout generation), and develop Python-based tools to automate the design-to-wafer pipeline and reduce manual handoff errors.
Failure analysis coordination & continuous improvement
- Coordinate the investigation of device failures at room and cryogenic temperatures using electrical test data, inline metrology, and advanced microscopy (SEM, AFM).
- Lead corrective and preventive actions using structured problem-solving methodologies (5 Whys, Ishikawa).
Requirements
- Master's degree or Ph.D. in Physics, Materials Science, or a related field.
- 3+ years of hands-on experience in semiconductor or superconducting circuit nanofabrication or process integration.
- Proven expertise in yield engineering, SPC, DOE, and statistical analysis tools.
- Proficiency in Python scripting to adapt and extend tools connecting design and fabrication workflows.
- Strong problem-solving mindset and command of root cause analysis methodologies (5 Whys, FMEA, Ishikawa).
- Excellent communication skills and the ability to work effectively in a cross-disciplinary environment.
- Experience in the fabrication or characterization of superconducting circuits, or in cryogenic testing is a plus.
Recruitment Process
- Screening Call with Alexandra, Talent Acquisition Specialist (30 min)
- Hiring Manager Interview with Alireza (45 min)
- Technical Interview/Presentation with the Team (120 min)
- Leadership Team Interview (45 min)
- Fit Interview (45 min)
- Reference check
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Benefits:
- Our success is your success: own it with our BSPCE plan
- Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
- Flexible remote policy, up to 40 % a month
- A Parental plan including additional benefits such as crèche support or additional days-off to take care of under 12 years old children
- Subsidized membership withUrban Sports Club
- Mental health support with moka.care
- 25-day vacation policy (as per French law) + RTT
- Half of transportation cost coverage (as per French law), or yearly allowance for the die-hard bicycle users
- Competitive health coverage, with Alan.
- Meal vouchers with Swile, as well as access to a fully equipped and regularly stocked kitchen
- French language courses covered by the company for those interested
Research shows that women might feel hesitant to apply for this job if they don't match 100% of the job requirements listed. This list is a guide, and we'd love to receive your application even if you think you're only a partial match. We are looking to build teams that innovate, not just tick boxes on a job spec.
You will join of one of the most innovative startups in France at an early stage, to be part of a passionate and friendly team on its mission to build the first universal quantum computer!
We love to share and learn from one another, so you will be certain to innovate, develop new ideas, and have the space to grow.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The transition of superconducting quantum processing units from laboratory prototypes to fault-tolerant architectures hinges on overcoming yield and integration bottlenecks in nanofabrication. Senior Integration and Yield Engineers operate at the critical nexus of chip design, process node development, and statistical process control to stabilize circuit performance across multi-qubit physical layouts. As the deep-tech sector moves toward commercial-scale manufacturing, maintaining tight parametric uniformities—such as Josephson junction critical currents and qubit resonance frequencies—is essential to preventing physical defects from degrading systemic gate fidelity. By establishing statistical data baselines and bridging design-to-fab handoffs, this role type mitigates non-reproducibility risks, enabling hardware developers like Alice & Bob to scale physical qubit density predictably without compounding fabrication defects.
Within the global quantum hardware ecosystem, the integration layer represents a primary structural bottleneck determining the commercial viability of fault-tolerant processors. While classical semiconductor foundries rely on highly standardized, mature process nodes, superconducting circuit fabrication operates at an earlier Technology Readiness Level (TRL) where process variations directly impact quantum coherence and error rates. The scaling of solid-state quantum processors requires transitioning from ad-hoc laboratory fabrication routines to rigorous, statistical-process-control-driven foundry workflows.
Ecosystem growth is currently constrained by the translation gap between high-level electromagnetic layout designs and physical wafer-scale execution. Non-uniformity in thin-film deposition, lithographic patterning, and junction oxidation introduces severe parameter spread across single wafers, leading to frequency crowding and crosstalk in complex processor architectures. To resolve these challenges, the sector depends heavily on integration methodologies adapted from advanced semiconductor manufacturing, including Design for Manufacturability (DFM) and automated layout pipelines.
Furthermore, supply chain resilience and capital efficiency in deep-tech hardware ventures depend on maximizing wafer-level yield. As physical qubit counts scale from dozens to hundreds, random and systematic defect density must be systematically driven toward zero to avoid cost-prohibitive fabrication cycles. Process integration functions act as the central operational bridge that reconciles quantum physical constraints with modern foundry capabilities, ensuring that physical hardware roadmaps remain on a deterministic trajectory toward fault tolerance.
The technical architecture for process integration in superconducting quantum circuits relies on linking statistical yield engineering with nanofabrication workflows. Central to this capability is the creation of automated layout tools and parameter lookup tables that map physical layout parameters directly to targeted cryogenic device characteristics. Establishing robust Design Rule Manuals (DRM) and Design for Manufacturability (DFM) frameworks allows hardware engineering teams to enforce structural rules that prevent lithographic and etch variations from impacting circuit functionality.
Additionally, continuous yield improvement depends on integrated data pipelines capable of ingesting high-volume wafer metrology, inline room-temperature electrical probing, and low-temperature cryogenic characterization data. Performing advanced statistical process control, design of experiments (DOE), and root-cause failure analysis via inline SEM and AFM metrology ensures that systematic process detractors are rapidly identified and rectified. These capabilities minimize iteration friction between circuit designers and nanofabrication foundries, stabilizing process baselines and accelerating the overall hardware deployment cycle for developers like Alice & Bob. - Accelerates the transition from experimental nanofabrication prototypes to standardized, foundry-grade quantum circuit production
- Mitigates systematic parameter spread to preserve intended qubit operating frequencies and coherence dynamics across large wafer layouts
- Facilitates seamless design-to-fabrication handoffs by automating layout generation and parameter mapping pipelines
- Strengthens physical device reliability through the implementation of rigorous statistical process control frameworks
- Reduces capital expenditure and wafer wastage by systematically identifying and eliminating root causes of yield loss
- Establishes scalable Design for Manufacturability guidelines tailored to superconducting and Josephson junction fabrication processes
- Optimizes cryogenic testing throughput by aligning room-temperature inline metrology with low-temperature device performance metrics
- Enhances cross-functional alignment between theoretical qubit architecture teams and cleanroom process engineering groups
- Improves the predictability of physical hardware scaling timelines for fault-tolerant quantum computing architectures
- Standardizes process of reference documentation to ensure repeatable manufacturing across internal and external foundry facilities
- Stabilizes wafer-scale inductance and frequency targeting to prevent spectral crowding in multi-qubit processors
- Protects capital investments in advanced cleanroom infrastructure by maximizing functional die yields per wafer runIndustry Tags: Superconducting Quantum Circuits, Process Integration, Yield Engineering, Nanofabrication, Statistical Process Control, Design for Manufacturability, Josephson Junctions, Wafer Metrology, Fault-Tolerant Quantum Hardware
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