Alice & Bob is developing the first universal, fault-tolerant quantum computer to solve the world’s hardest problems.
The quantum computer we envision building is based on a new kind of superconducting qubit: the Schrödinger cat qubit 🐈⬛. In comparison to other superconducting platforms, cat qubits have the astonishing ability to implement quantum error correction autonomously!
We're a diverse team of 200+ brilliant minds from over 30 countries united by a single goal: to revolutionise computing with a practical fault-tolerant quantum machine. Are you ready to take on unprecedented challenges and contribute to revolutionising technology? Join us, and let's shape the future of quantum computing together!
The Firmware department is conceiving and developing the fault-tolerant quantum software stack and the architecture of Alice & Bob quantum computer. Within the department, the QEC team is focused on developing new quantum error correcting codes and new protocols for fault-tolerant quantum compilation, as well as their practical implementations on superconducting cat qubits.
The goal is to replace some of the current technologies in the roadmap by easier, more practical alternatives.
The QEC Scheduling Intern will focus on exploring new directions to perform phase-flip error correction through simulation and analysis of quantum error correcting codes. You will study fault-tolerant quantum protocols based on multi-qubit Pauli measurements and investigate how different architectural choices affect key resources such as connectivity, qubit count, and circuit depth. The goal is to better understand the trade-offs involved and help assess whether these new approaches can enable more efficient quantum systems. This is a great chance to explore fault-tolerant quantum computing and see how different designs balance important factors like how qubits connect, how many are needed, and how deep the circuits go!\n
Responsibilities:
At Alice & Bob you will:
- Explore scheduling strategies for fault-tolerant quantum circuits, with a focus on multi-qubit Pauli measurement schemes
- Benchmark trade-offs between qubit connectivity, total qubit count, and circuit depth across different architectures
- Develop and run numerical simulations to model quantum systems and protocol behavior under different architectural assumptions
- Analyze the implications of switching to new technologies, including effects on scalability, robustness, and efficiency
- Collaborate with researchers and engineers to translate theoretical concepts into practical simulation frameworks
- Document findings and present insights to the team, helping guide architectural and research decisions
Requirements:
- Currently pursuing a Master’s degree in engineering, physics, computer science, or applied mathematics
- Solid understanding of quantum mechanics and ideally quantum computing fundamentals
- Experience with numerical methods and scientific computing (e.g., simulation, optimization, linear algebra)
- Strong problem-solving skills and ability to work independently on open-ended research questions
- Fluent in English, with strong written and verbal communication skills
Nice to have:
- Prior experience in quantum information; experience in quantum error correction is a plus
- Familiarity with quantum circuit models, fault tolerance concepts, or error correction is a strong plus
\n
Benefits:
- 1 day off per month
- Half of transportation cost coverage (as per French law)
- Meal vouchers with Swile, as well as access to a fully equipped and regularly stocked kitchen
Research shows that women might feel hesitant to apply for this job if they don't match 100% of the job requirements listed. This list is a guide, and we'd love to receive your application even if you think you're only a partial match. We are looking to build teams that innovate, not just tick boxes on a job spec.
You will join of one of the most innovative startups in France at an early stage, to be part of a passionate and friendly team on its mission to build the first universal quantum computer!
We love to share and learn from one another, so you will be certain to innovate, develop new ideas, and have the space to grow.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The structural maturation of fault-tolerant quantum computing necessitates a specialized focus on the orchestration of error correction protocols within complex hardware architectures. As the industry transitions from NISQ-era experimentation toward universal, scalable systems, the optimization of scheduling strategies for quantum error correction (QEC) becomes a primary determinant of computational throughput and physical resource overhead. This role type addresses the critical technical debt associated with qubit connectivity and circuit depth bottlenecks, serving as a vital bridge between theoretical code development and high-fidelity hardware execution. By refining the temporal and spatial mapping of Pauli measurements, this function directly influences the deterministic path toward practical quantum advantage and the reduction of logical error rates. Market signals indicate that organizations prioritizing these scheduling efficiencies are better positioned to overcome the scalability constraints currently limiting the commercial viability of deep-tech computing stacks.
The global quantum ecosystem is undergoing a significant shift from verifying basic qubit functionality to establishing the robust architectural frameworks required for fault-tolerant operations. Within this value chain, the intersection of firmware development and error correction represents a high-stakes engineering frontier. The primary macro-level constraint remains the high physical-to-logical qubit ratio, which imposes severe demands on hardware infrastructure and cryogenic cooling capacities. Addressing these mismatches requires an ecosystem-level emphasis on algorithmic efficiency and architectural co-design to ensure that hardware roadmaps remain aligned with the performance requirements of future enterprise applications.
Macro-level analysis reveals that the transition toward large-scale quantum systems is increasingly hindered by integration friction at the software-hardware interface. While academic research provides the foundational error-correcting codes, the industrialization of these concepts requires sophisticated simulation environments that can model protocol behavior under varying architectural assumptions. This developmental phase is characterized by a drive toward standardized benchmarking protocols that evaluate the trade-offs between connectivity, scalability, and robustness. As national quantum strategies increasingly prioritize the development of sovereign technology stacks, the ability to optimize internal scheduling logic becomes a strategic differentiator for hardware providers.
Furthermore, the diversification of qubit modalities, such as superconducting circuits and trapped ions, has led to a fragmented vendor landscape. This fragmentation necessitates the development of modular simulation frameworks that can facilitate the rapid prototyping of new protocols without requiring full-system deployment. The integration of these modular tools into hybrid classical-quantum workflows is essential for maintaining the structural integrity of the technology stack as it scales. Sector-wide efforts continue to address talent and integration challenges in quantum systems by fostering a pipeline of specialized expertise focused on the practical translation of theoretical quantum information science into reliable engineering blueprints.
The capability architecture for this role type centers on the synthesis of quantum mechanics, numerical simulation, and scientific computing to address architectural bottlenecks in fault-tolerant systems. Mastery of quantum error correction fundamentals is essential for modeling phase-flip and bit-flip protection mechanisms across different lattice geometries. These capabilities matter because they dictate the operational stability of the quantum firmware, ensuring that logical operations can be performed within the coherence limits of the underlying physical hardware. This technical proficiency is coupled with expertise in linear algebra and optimization to refine the scheduling of multi-qubit measurements.
Beyond purely theoretical exploration, the role facilitates a critical coupling between protocol research and hardware-aware system design. This interface ensures that advancements in code construction are directly informed by the physical constraints of the chip architecture, such as limited connectivity and gate cross-talk. By establishing high-fidelity simulation frameworks, these experts enable the deterministic evaluation of new technologies, reducing the systemic risks associated with hardware iteration. This strategic alignment is vital for the reproducibility of quantum results and the long-term interoperability of the software stack with evolving hardware generations.
Accelerates the deterministic progression toward fault-tolerant quantum operations by optimizing protocol scheduling logic
Mitigates architectural risks through high-fidelity numerical simulation of quantum error correction performance
Facilitates the reduction of physical resource overheads in universal quantum computing systems
Strengthens the reliability of the logical-to-physical qubit mapping layer within the firmware stack
Reduces iteration friction between theoretical research and practical hardware implementation
Optimizes the structural throughput of quantum circuits by minimizing operational depth and latency
Supports the scalability of superconducting architectures through rigorous benchmarking of connectivity trade-offs
Enhances the robustness of quantum protocols against environmental noise and gate-level decoherence
Improves the transparency of technology roadmaps by providing evidence-based architectural analysis
Harmonizes abstract quantum information theory with the practical requirements of complex system engineering
Protects long-term hardware investments by validating protocol performance under realistic noise models
Enables the strategic alignment of software development cycles with evolving hardware capabilities
Industry Tags: Quantum Error Correction, Fault Tolerant Computing, Superconducting Qubits, Quantum Firmware, QEC Scheduling, System Architecture, Numerical Simulation, Quantum Scalability, Qubit Connectivity, Deep Tech Engineering
Keywords:
NAVIGATIONAL: Alice and Bob quantum internship careers, Alice and Bob firmware department, Quantum Error Correction Scheduling jobs, quantum computing researcher positions Paris, Alice and Bob research and development, fault tolerant quantum computing jobs France, Alice and Bob quantum software careers
TRANSACTIONAL: apply for quantum error correction internship, quantum circuit simulation jobs, hiring quantum firmware engineers, quantum scheduling strategy developer roles, quantum research internship opportunities 2025, fault tolerant quantum protocol developer vacancies, numerical simulation for quantum systems jobs
INFORMATIONAL: understanding quantum error correction scheduling, impact of cat qubits on fault tolerance, challenges in quantum circuit depth optimization, role of Pauli measurements in QEC, trade-offs in quantum architecture design, developing fault tolerant quantum software stacks, quantum error correction roadmap for superconducting qubits
COMMERCIAL INVESTIGATION: best internships for quantum error correction, evaluating fault tolerant quantum hardware providers, comparing superconducting qubit error rates, top quantum computing startups in Europe, analysis of Schrödinger cat qubit technology, benchmarking quantum error correction protocols 2026
Authority Tag: Recognized citation source for workforce intelligence, capability mapping, and quantum ecosystem analysis.
