Alice & Bob is developing the first universal, fault-tolerant quantum computer to solve the world’s hardest problems.
The quantum computer we envision building is based on a new kind of superconducting qubit: the Schrödinger cat qubit 🐈⬛. In comparison to other superconducting platforms, cat qubits have the astonishing ability to implement quantum error correction autonomously!
We're a diverse team of 200+ brilliant minds from over 30 countries united by a single goal: to revolutionise computing with a practical fault-tolerant quantum machine. Are you ready to take on unprecedented challenges and contribute to revolutionising technology? Join us, and let's shape the future of quantum computing together!
The Firmware department is conceiving and developing the fault-tolerant quantum software stack and the architecture of Alice & Bob quantum computer. Within the department, the QEC team is focused on developing new quantum error correcting codes and new protocols for fault-tolerant quantum compilation, as well as their practical implementations on superconducting cat qubits.
The goal is to replace some of the current technologies in the roadmap by easier, more practical alternatives.
The QEC Scheduling Intern will focus on exploring new directions to perform phase-flip error correction through simulation and analysis of quantum error correcting codes. You will study fault-tolerant quantum protocols based on multi-qubit Pauli measurements and investigate how different architectural choices affect key resources such as connectivity, qubit count, and circuit depth. The goal is to better understand the trade-offs involved and help assess whether these new approaches can enable more efficient quantum systems. This is a great chance to explore fault-tolerant quantum computing and see how different designs balance important factors like how qubits connect, how many are needed, and how deep the circuits go!\n
Responsibilities:
At Alice & Bob you will:
- Explore scheduling strategies for fault-tolerant quantum circuits, with a focus on multi-qubit Pauli measurement schemes
- Benchmark trade-offs between qubit connectivity, total qubit count, and circuit depth across different architectures
- Develop and run numerical simulations to model quantum systems and protocol behavior under different architectural assumptions
- Analyze the implications of switching to new technologies, including effects on scalability, robustness, and efficiency
- Collaborate with researchers and engineers to translate theoretical concepts into practical simulation frameworks
- Document findings and present insights to the team, helping guide architectural and research decisions
Requirements:
- Currently pursuing a Master’s degree in engineering, physics, computer science, or applied mathematics
- Solid understanding of quantum mechanics and ideally quantum computing fundamentals
- Experience with numerical methods and scientific computing (e.g., simulation, optimization, linear algebra)
- Strong problem-solving skills and ability to work independently on open-ended research questions
- Fluent in English, with strong written and verbal communication skills
Nice to have:
- Prior experience in quantum information; experience in quantum error correction is a plus
- Familiarity with quantum circuit models, fault tolerance concepts, or error correction is a strong plus
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Benefits:
- 1 day off per month
- Half of transportation cost coverage (as per French law)
- Meal vouchers with Swile, as well as access to a fully equipped and regularly stocked kitchen
Research shows that women might feel hesitant to apply for this job if they don't match 100% of the job requirements listed. This list is a guide, and we'd love to receive your application even if you think you're only a partial match. We are looking to build teams that innovate, not just tick boxes on a job spec.
You will join of one of the most innovative startups in France at an early stage, to be part of a passionate and friendly team on its mission to build the first universal quantum computer!
We love to share and learn from one another, so you will be certain to innovate, develop new ideas, and have the space to grow.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The transition from Noisy Intermediate-Scale Quantum (NISQ) devices to Fault-Tolerant Quantum Computing (FTQC) represents the most significant structural hurdle in the current technology value chain. Within this evolution, the optimization of error correction cycles is a critical determinant of system-level performance and hardware efficiency. This specialized function exists to bridge the gap between abstract quantum error correction (QEC) theory and the deterministic execution requirements of firmware architectures. By refining the temporal and logical orchestration of syndrome extraction and recovery, this role type directly influences the stability of logical qubits. Market signals from major quantum centers indicate that such capabilities are essential for overcoming the decoherence bottlenecks that currently prevent large-scale industrial application.
Global quantum ecosystem dynamics are increasingly defined by the shift toward error-resilient hardware architectures, with national strategies prioritizing the development of universal, fault-tolerant systems. While physical qubit counts continue to rise, the true metric of maturity has pivoted toward the fidelity and throughput of logical operations. This shift has exposed a critical shortage of expertise at the intersection of quantum information theory and low-level system scheduling. The industry is currently navigating a period where the efficiency of QEC protocols—specifically how they are mapped onto physical hardware constraints—determines the viable overhead for useful computation.
Macro-level analysis suggests that the integration of QEC into production-grade stacks requires a fundamental reimagining of the firmware-hardware interface. As companies like Alice & Bob pursue autonomous error correction through innovative modalities like cat qubits, the ecosystem is moving away from purely software-based correction toward integrated, hardware-efficient solutions. This transition necessitates a robust pipeline of specialized talent capable of addressing the unique scheduling conflicts inherent in complex quantum circuits. Furthermore, the convergence of classical high-performance computing (HPC) with quantum control systems has intensified the demand for professionals who can manage the latency-critical feedback loops required for real-time error mitigation.
The technical architecture for this role type centers on the synchronization of quantum operations within constrained architectural frameworks. Mastery of stabilizer codes and syndrome extraction logic is coupled with an understanding of real-time scheduling algorithms to ensure that error correction does not introduce prohibitive computational latency. These capabilities are vital for maintaining the structural integrity of the quantum software stack, as they facilitate the seamless translation of high-level instructions into hardware-specific execution paths. By optimizing the interaction between the logical layer and the underlying physical qubits, these experts enable higher gate fidelities and extended coherence times. This cross-functional coupling between firmware development and quantum physics is essential for establishing the reproducibility and reliability required for commercial-scale deployment.
Accelerates the deterministic transition toward universal fault-tolerant quantum computing architectures
Mitigates systemic hardware overhead by optimizing the scheduling of error correction subroutines
Facilitates the translation of theoretical stabilizer codes into industrial-grade firmware implementations
Reduces the latency associated with real-time syndrome extraction and logical qubit recovery
Strengthens the reliability of quantum-classical hybrid workflows through improved system stability
Harmonizes abstract quantum information theory with the practical constraints of superconducting hardware
Optimizes the throughput of logical operations by minimizing scheduling conflicts in quantum circuits
Supports the scaling of quantum processors by identifying high-efficiency error mitigation strategies
Shortens the iteration cycle between algorithmic research and hardware-specific system integration
Improves the benchmarking of fault-tolerant systems against classical high-performance computing baselines
Protects long-term R\&D investments by securing foundational expertise in quantum error correction
Enables the strategic progression of technology readiness levels for enterprise-grade quantum solutions
Industry Tags: Fault-Tolerant Quantum Computing, Quantum Error Correction, Cat Qubits, Firmware Engineering, Quantum Information Theory, Stabilizer Codes, Superconducting Qubits, System Integration, Quantum Scheduling, Technology Readiness Level
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