Working closely with system architects, digital designers, and experimental physicists, you will translate system-level requirements into robust circuit implementations while driving performance across the control stack—all while contributing individually and empowering others on the team. Design and develop CMOS analog circuits and functional blocks for quantum control applications Contribute to the architecture and specification of Cryo-CMOS subsystems in collaboration with system and hardware teams Perform simulation verification of full-custom analog and mixed-signal designs Collaborate with cross-functional teams to optimize system-level tradeoffs across analog, digital, and cryogenic domains Support bring-up and characterization of ASICs, including integration with system-level control hardware Document designs, results, and methodologies to enable reproducibility, knowledge sharing, and downstream integration Contribute to technical publications and internal reports as appropriate Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 6+ years of technical engineering experience OR Master's degree in Electrical Engineering, Computer Engineering, or related field and 4+ years of technical engineering experience OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field and 1+ years of technical engineering experience OR equivalent experience Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation). Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development. 10+ years of industry experience in analog or mixed-signal design delivering complex systems, including 4+ years designing, simulating, and laying out CMOS analog circuits Deep experience with analog and mixed-signal Electronic Design Automation tools (e.g., Cadence Virtuoso) and proficiency with scripting/programming languages and Linux-based development environments Experience designing analog building blocks such as Analog-to-Digital Converters, Digital-to-Analog Converters, Phase-Locked Loops, and Radio Frequency components Familiarity with digital design and verification languages (e.g., Verilog/SystemVerilog) and signal integrity considerations in high-performance systems Experience with cryogenic circuit design, low-temperature measurements, semiconductor behavior at cryogenic temperatures, and quantum device interfaces, including hands-on ASIC bring-up, characterization, and lab validation with system-level hardware Strong communication, documentation, and cross-team collaboration skills, with a track record of technical publications or internal reporting and the ability to operate effectively in fast-paced research environments
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The structural advancement of large-scale quantum processors is currently impeded by the thermal and volumetric constraints of room-temperature control cabling, a challenge commonly identified as the wiring bottleneck. To achieve the million-qubit regimes required for fault-tolerant operation, the quantum ecosystem necessitates a transition toward integrated cryogenic control architectures that can operate within the stringent power budgets of dilution refrigerators. This role type exists to bridge the gap between fundamental semiconductor physics and the engineering of scalable quantum hardware by developing specialized CMOS electronics that function at millikelvin temperatures. By localizing control and readout functions close to the quantum core, this function enables the massive parallelization of qubit operations essential for industrial-grade utility. Market signals indicate that the ability to architect these integrated cryogenic subsystems is a primary determinant for the commercial viability of high-qubit-count systems.
The emergence of cryo-CMOS integrated circuits represents a critical pivot in the quantum technology value chain, transitioning from laboratory-scale experiments with discrete components toward consolidated, industrial-grade hardware stacks. As the sector moves from noisy intermediate-scale quantum devices to error-corrected architectures, the demand for high-fidelity control interfaces grows exponentially. This shift necessitates a specialized tier of analog and mixed-signal engineering focused on the unique behavioral characteristics of semiconductors at cryogenic temperatures, where classical modeling often fails and power dissipation becomes a non-negotiable constraint.
Macro-level analysis of the global quantum landscape reveals that the "control bottleneck" is now a leading systemic risk for hardware developers. While qubit coherence times continue to improve, the physical infrastructure required to manage those qubits remains bulky and energy-intensive. Organizations are responding by integrating deep-tech IC design expertise directly into their quantum research centers, aiming to develop custom application-specific integrated circuits (ASICs) that replace kilometers of coaxial cabling with localized, low-power silicon solutions.
Furthermore, the maturation of this domain depends on the development of new Electronic Design Automation toolchains and characterization methodologies tailored for 4K and sub-1K environments. This requirement places the role at the center of a complex supply chain involving specialized foundries, cryogenic infrastructure providers, and system-level software architects. As the industry scales, the ability to synchronize these diverse technical layers will define the trajectory of sovereign and commercial quantum roadmaps alike.
The capability architecture for this role centers on the convergence of precision analog design and cryogenic device physics. At the foundational layer, mastery of building blocks such as high-speed data converters, frequency synthesizers, and low-noise amplifiers is essential for ensuring high-fidelity qubit manipulation. These technical proficiencies must be adapted for ultra-low temperature regimes, requiring a deep understanding of carrier freeze-out, thermal noise floors, and power density limits. This technical layer provides the structural leverage needed to reduce the physical footprint of the quantum control stack while maintaining the signal integrity required for gate operations.
Beyond circuit-level execution, the role facilitates a critical coupling between system architecture and physical hardware reality. By translating abstract performance requirements into validated silicon implementations, these experts enable the deterministic scaling of quantum processors. The interface between analog signal processing and digital control logic represents a primary integration point where system-level tradeoffs—such as bandwidth versus power consumption—are resolved. These capabilities are vital for the long-term interoperability of modular quantum subsystems, ensuring that emerging hardware remains compatible with the evolving requirements of error correction and hybrid classical-quantum workflows.
Accelerates the deterministic progression of technology readiness levels for integrated cryogenic control hardware
Mitigates systemic risks associated with the wiring bottleneck in large-scale quantum processor architectures
Facilitates the transition from bulky room-temperature control racks to compact localized silicon solutions
Reduces signal latency and thermal load within dilution refrigerators through advanced circuit integration
Strengthens the competitive positioning of hardware providers by enabling the management of higher qubit counts
Harmonizes precision analog design with the stringent power constraints of millikelvin environments
Optimizes the fidelity of qubit control and readout through specialized low-noise circuit architectures
Supports the scaling of fault-tolerant quantum computing by providing the necessary control infrastructure
Shortens the development cycles for quantum-specific ASICs through the application of advanced modeling
Improves the reliability of quantum-classical hardware interfaces through rigorous simulation and verification
Protects capital-intensive investments in quantum hardware by ensuring the scalability of the control stack
Enables the strategic orchestration of cross-functional hardware teams through standardized architectural interfaces
Industry Tags: Cryo-CMOS, Analog IC Design, Quantum Control Systems, Mixed-Signal ASICs, Dilution Refrigeration, Scalable Quantum Hardware, Qubit Interface, Semiconductor Physics
Keywords:
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