Your responsibilities will include interfacing and establishing relationships with internal/external foundries, and creation of library Process-Development-Kits (PDK) for Cryo/Quantum System-on-a-Chip (SOC) implementation. Evaluate their solutions for materials/process tailoring to match our needs. Create long-term evolution plans with vendors for evolving process needs for future quantum products. Find / define design development libraries and re-characterizations for standard cells and analog design PDKs at cryo temperatures. Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization. Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions; practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment OR equivalent experience 5+ years of experience in device physics, foundry design collateral, process qualification, broad fabrication process experience, device reliability, statistical analysis, yield improvement, and physical failure analysis techniques. Experience with device-level measurements and associated test equipment, data analysis, modeling, simulation, targeting and projection. Experience in Leading cross-functional teams and understands program/project management. Proficient in product yield/performance analysis, and design technology co-optimization. Proficient in data analysis tools like excel, JMP, etc. Coding using various languages including but not limited to Python, Java and C++ Leveraging and designing/optimizing Artificial Intelligence/Machine Learning (AI/ML) Design for Testability (DFT) and Design for Manufacturability (DFM) techniques 9+ years of related technical engineering experience with a BSEE equivalent or higher in Electrical Engineering, Material Science or related field. 8 + years of experience in semiconductor process development and manufacturing. 5+ years of experience in and technology evaluation, testchip and modeling. Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation). Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The structural maturation of fault-tolerant quantum computing necessitates a specialized tier of leadership at the intersection of semiconductor manufacturing and cryogenic electronics. As the industry transitions from laboratory prototypes to industrial-scale production, the role of a Senior Quantum Foundry Technologist serves as a critical bridge between theoretical device physics and high-volume foundry operations. This function addresses the fundamental "wiring bottleneck" and integration challenges inherent in scaling qubits within dilution refrigerators. By orchestrating the development of cryogenic process design kits, this role type ensures that emerging hardware architectures remain compatible with the rigorous standards of global semiconductor supply chains. Market signals indicate that securing this hybrid expertise in both foundry ecosystems and quantum systems is a primary determinant for organizations aiming to lead the first wave of commercial-grade quantum utility.
The quantum hardware sector is currently navigating a critical inflection point where the availability of stable, scalable qubits depends on the transition from specialized research labs to standardized commercial foundries. This shift represents a move from custom-fabricated components to the adoption of sophisticated Process Development Kits (PDKs) specifically optimized for cryogenic environments. While the classical semiconductor industry has spent decades refining room-temperature reliability, the unique thermal and volumetric constraints of quantum systems create a significant Technology Readiness Level mismatch. Current industry focus lies on bridging classical and quantum capabilities at scale by adapting existing CMOS processes for sub-Kelvin operation.
Macro-level analysis of the global quantum value chain reveals that the ability to establish resilient, long-term relationships with external foundries is becoming a national strategic imperative. Organizations are no longer operating in isolation; they are part of a fragmented but rapidly consolidating ecosystem of vendors, toolmakers, and material scientists. This environment favors role types that can synchronize internal hardware roadmaps with the lead times and process evolutions of global semiconductor giants. The scarcity of talent capable of managing these high-authority interfaces represents a systemic risk to the timely deployment of million-qubit systems.
Furthermore, the integration of modular quantum control stacks requires a structural shift in how testchips and engineering structures are designed. The industry is moving away from purely empirical data collection toward predictive, AI-enhanced performance modeling. This transition is essential for reducing iteration cycles in hardware development and ensuring that future quantum System-on-a-Chip (SoC) architectures are manufacturable and yield-stable. As national quantum strategies prioritize domestic manufacturing capabilities, the role of the foundry specialist becomes vital for securing first-mover advantage in the emerging deep-tech economy.
The capability architecture for this role type centers on the synchronization of device-level measurements with large-scale semiconductor process qualification. At the foundational layer, mastery of cryogenic CMOS library development and standard cell re-characterization is essential for ensuring the integrity of the control stack at millikelvin temperatures. This technical proficiency is coupled with a deep understanding of Design for Manufacturability (DFM) and Design for Testability (DFT), which are critical for the structural throughput of quantum research. These capabilities allow for the translation of high-fidelity qubit requirements into stable, silicon-verified PDKs that can be deployed across a variety of hardware modalities.
Beyond technical execution, the role facilitates a high-level coupling between silicon characterization and enterprise-ready hardware roadmaps. This interface ensures that advancements in material science—such as selective depositions or improved dielectric interfaces—are successfully intercepted by current fabrication cycles. By standardizing the creation of design development libraries, these experts enable a level of operational readiness that allows Microsoft and its partners to navigate the complexities of deep cryogenic integration. This strategic alignment is vital for maintaining the competitive trajectory of the platform as it scales toward universal fault tolerance.
Accelerates the deterministic progression of technology readiness levels for cryogenic semiconductor architectures
Mitigates systemic risks in the quantum hardware supply chain by establishing robust foundry partnerships
Facilitates the transition from experimental qubit prototypes to standardized commercial-grade manufacturing
Reduces iteration friction in the hardware design cycle through the development of cryogenic PDKs
Strengthens the long-term competitive positioning of quantum platforms through superior yield optimization
Harmonizes abstract device physics with the practical requirements of industrial-grade semiconductor fabrication
Optimizes the lifecycle of quantum systems through the integration of AI-driven performance modeling
Supports the scaling of quantum processors by addressing the thermal and volumetric constraints of cryogenic wiring
Shortens the time-to-market for fault-tolerant systems by ensuring infrastructure alignment with foundry roadmaps
Improves the reliability of cryogenic control electronics through rigorous model-silicon characterization
Protects capital-intensive investments in hardware R\&D by providing expert technical validation of process tailoring
Enables the strategic orchestration of development efforts across complex networks of internal and external stakeholders
Industry Tags: Quantum Foundry, Cryogenic CMOS, Semiconductor Manufacturing, PDK Development, System-on-a-Chip, Hardware Scalability, Device Physics, Technology Readiness Level, Quantum Systems Integration
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