ASIC Design Engineer
Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams to build a cutting-edge control stack for industrial-scale quantum computers.
Our distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high-frequency analog signals. Imagine what it takes to talk to 10,000 qubits with
nanosecond-level synchronization and all-to-all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon.
We foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed-signal engineers, digital verification specialists, embedded software developers, and physicists.
Your Role:
Deconstruct Requirements & Design: Evaluate system requirements to
architect and implement robust, high-performance digital logic and IP
blocks.
Front-End Flow Ownership: Drive designs through the front-end ASIC
flow, including RTL coding, linting, clock domain crossing (CDC)
analysis, and initial synthesis.
Verification Collaboration: Write block-level self-checking testbenches
and collaborate with the verification team to expand top-level UVM
environments.
Architectural Influence: Propose innovative changes to chip
architecture, power-saving strategies, and team methodologies.
Cross-Functional Sparring: Act as a core technical sparring partner to a
diverse engineering team, continuously pushing for better ways of doing
things.
Enough about us, what about you?
To thrive in this role, you should bring:
Experience: 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape-outs/deliveries.
RTL & Architecture: Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.
EDA Tools & Flow: Strong experience with standard ASIC front-end EDA tools, processor/bus-system architectures (e.g., AMBA AXI/AHB protocols), and synthesis.
Timing & Constraints: Solid understanding of static timing analysis (STA) constraints and timing closure methodologies.
Mixed-Signal Familiarity: Understanding of analog/mixed-signal chips or IP (e.g., ADC/DAC interfaces, PLLs).
Automation & Tools: Proficiency in scripting to automate design workflows (Python, Tcl, Shell) and version control (Git).
Communication: Strong communication and collaboration skills.
Optional Nice-to-Haves:
Active experience with advanced verification frameworks (UVM).
Prior experience with DFT (Design for Test) insertion, scan chains, and BIST.
Experience with modelling and simulation in MATLAB / Simulink.
Strong background in DSP and signal-processing filters.
Familiarity with AI agentic workflows and automation within the design flow.
Experience or a strong interest in the Quantum Computing field.
TECHNICAL & MARKET ANALYSIS | Appended by Quantum.Jobs
The shift from general-purpose high-performance computing to domain-specific quantum control architectures has created a critical structural requirement for Senior ASIC Design Engineers. As the industry moves toward 10,000-qubit targets, the transition from off-the-shelf components to dedicated silicon is essential for managing the nanosecond-level synchronization and massive data throughput required for error-corrected quantum systems. This role type serves as a primary stabilization point in the hardware value chain, converting complex physical requirements into scalable, deterministic integrated circuits. By mitigating the power and latency bottlenecks of classical control stacks, these experts enable the physical realization of fault-tolerant roadmaps. Market signals from major technology hubs indicate that this capability is the decisive factor in overcoming the scalability "valley of death" for commercial quantum hardware providers.
The quantum hardware ecosystem is currently navigating a pivotal transition from laboratory prototypes to industrial-scale modular architectures. A primary macro constraint is the "control bottleneck," where the classical electronics required to manipulate qubits consume disproportionate power and physical space relative to the quantum processor. To address this, the sector is increasingly prioritizing the development of custom application-specific integrated circuits (ASICs) that can operate in close proximity to the quantum environment. This shift is critical for reducing signal latency and improving the fidelity of qubit readout and control operations across high-density arrays.
Current industry focus lies on bridging classical and quantum capabilities at scale, which requires a deep integration of heterogeneous technologies. The move toward dedicated silicon represents a maturation of the supply chain, as vendors move away from flexible but inefficient FPGA-based solutions toward optimized ASICs. This evolution is mirrored in national quantum strategies which emphasize "sovereign" semiconductor capabilities to secure the underlying infrastructure of the emerging quantum economy. However, the scarcity of senior-level digital design talent with exposure to mixed-signal environments remains a significant systemic risk to technology readiness level (TRL) progression.
Furthermore, the integration of these control stacks into existing high-performance computing (HPC) data centers introduces complex thermal and electromagnetic compatibility (EMC) requirements. As the value chain fragments into specialized layers—hardware modalities, control electronics, and software stacks—the role of the ASIC architect becomes that of a systems-level orchestrator. They must ensure that the digital logic not only meets rigorous timing constraints but also maintains interoperability with evolving quantum error correction protocols and hybrid classical-quantum workflows.
The capability architecture for this role type centers on the mastery of high-fidelity digital logic synthesis and complex front-end ASIC flows. Proficiency in Register Transfer Level (RTL) design using hardware description languages is the foundation for creating the IP blocks that drive qubit manipulation. Crucially, expertise in clock domain crossing (CDC) analysis and static timing analysis (STA) is required to manage the precise synchronization needed for gate operations across distributed architectures. These technical domains are the primary levers for ensuring system stability and minimizing the "noise" introduced by classical control electronics.
Beyond pure digital design, the interface between digital logic and analog/mixed-signal components—such as data converters and frequency synthesizers—is a vital throughput point. Understanding these coupling effects is essential for maintaining signal integrity in cryogenic or high-interference environments. Furthermore, the implementation of advanced verification frameworks, including Universal Verification Methodology (UVM), provides the structural reproducibility necessary to move from initial tape-outs to reliable, volume-produced silicon. This synchronization between microarchitecture and physical constraints is what allows the quantum ecosystem to transition from scientific experimentation to predictable, hardware-accelerated computation. - Accelerates the deterministic scaling of quantum control infrastructures from hundreds to thousands of qubits
- Mitigates systemic power consumption and thermal management risks within modular quantum hardware architectures
- Facilitates the transition from laboratory-scale control systems to production-grade dedicated silicon solutions
- Strengthens the reliability of qubit readout and control through high-precision nanosecond-level logic synchronization
- Reduces the physical footprint of quantum processors by integrating complex control logic into compact ASICs
- Optimizes the interoperability between classical high-performance computing environments and emerging quantum processing units
- Enhances the fidelity of quantum operations by minimizing latency and electronic noise in the control stack
- Supports the implementation of real-time quantum error correction protocols via high-speed digital signal processing
- Secures the hardware value chain by establishing robust, reproducible IP frameworks for quantum-specific integrated circuits
- Improves the cost-efficiency of industrial quantum systems by moving toward scalable semiconductor manufacturing processes
- Enables the synchronization of distributed quantum architectures through advanced multi-clock domain management
- Protects long-term research investments by providing a stable, high-performance foundation for software-hardware co-designIndustry Tags: ASIC Design, Quantum Control Systems, Semiconductor Engineering, Digital Logic, RTL Development, Scalable Hardware, Mixed-Signal Integration, Quantum Infrastructure, Fault Tolerance, Hardware Orchestration
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